下面是ieee文档自我提取的一些用法,这一篇的用法,更加全面:
1. covergroup常用用法;
covergroup cg_0;
cp_name coverpoint signal_name{
bins bin_name0 = {[0:63],65};//两个bin, [0:63],65, 只要有里面的值收到了,就全覆盖
bins bin_name1[] = { [127:150],[148:191] }; // 65个bin,即[]中的每一个值都是一个bin;
bins bin_name2 = { [1000:$] };//$表示结尾,即最大值;
bins bin_name3[] = default;//其他的所有值,都划分到other, 也是要全部都收到;
}
endgroup
2. bins with的用法;
cp_name: coverpoint signal_name{
bins bin_name[] = {[0:255]} with (item % 3 == 0);//0-255中3的余数为0的部分,构成bin;
}
也可以将with的内容封装成function;
coverpoint b {
bins func[] = b with (myfunc(item));
}
3. wildcard;
wildcard bins g12_15 = { 4'b11?? };//只要在1100~1111间的任何一个踩到了,就收到了;
wildcard bins g12_15_array[] = { 4'b11?? };//加了[], 会给每一个符合条件的都产生一个bin
4. ignore_bins;
当没有明确定义某一个coverpoint的bins时,EDA仿真工具会生成和收集所有可能的bins,当其中某些bins在RTL中永远都不可能覆盖到,可以使用ignore_bins进行忽略
covergroup cg23;
coverpoint a {
ignore_bins ignore_vals = {7,8};//不收集7,8;
ignore_bins ignore_trans = (1=>3=>5);//不收集1,3,5这个序列;
}
endgroup
5. illegal_bins;
某个值不可能收到,收到后报错;起到类似checker的作用;
covergroup cg3;
coverpoint b {
illegal_bins bad_vals = {1,2,3};
illegal_bins bad_trans = (4=>5=>6);
}
endgroup
6. cross;
bit [31:0] a_var;
bit [3:0] b_var;
covergroup cov3 @(posedge clk);
A: coverpoint a_var { bins yy[] = { [0:9] }; }
CC: cross b_var, A;//两个coverpoint进行cross;
endgroup
7. cross中指定bins;
int i,j;
covergroup ct;
coverpoint i { bins i[] = { [0:1] }; }
coverpoint j { bins j[] = { [0:1] }; }
x1: cross i,j;
x2: cross i,j {
bins i_zero = binsof(i) intersect { 0 };//i中不包含0;
//binsof(x) intersect (y);//x的取值中,只收取为y的值;
}
endgroup
8. binsof 与 && / ||的组合;
covergroup address_cov () @ (posedge ce);
ADDRESS : coverpoint addr {
bins addr0 = {0};
bins addr1 = {1};
}
CMD : coverpoint cmd {
bins READ = {0};
bins WRITE = {1};
bins IDLE = {2};
}
CRS_USER_ADDR_CMD : cross ADDRESS, CMD {
bins USER_ADDR0_READ = binsof(CMD) intersect {0};//默认的bins本来应该是2*3=6个,但是这里只定义了两个bins <addr0,READ> <addr1,READ>
bins u2 = binsof(ADDRESS.addr0) || binsof(CMD.READ);// bins 数目为4,包括<addr0,READ>,<addr0,WRITE>,<addr0,IDLE>,<addr1,READ>
bins u3 = binsof(ADDRESS.addr0) && binsof(CMD.READ);// bins 数目为1,包括<addr0,READ>
}
CRS_AUTO_ADDR_CMD : cross ADDRESS, CMD {
ignore_bins AUTO_ADDR_READ = binsof(CMD) intersect {0};
ignore_bins AUTO_ADDR_WRITE = binsof(CMD) intersect {1} && binsof(ADDRESS) intersect{0};
}
(原文链接:https://blog.csdn.net/bleauchat/article/details/90445713)
9. matches;
感觉上像是一个下线;
bins apple = X with (a+b < 257) matches 127;// 127~257?
10. 带参数的covergroup;
module mod_m;
logic [31:0] a, b;
covergroup cg(int cg_lim);
coverpoint a;
coverpoint b;
aXb : cross a, b {
function CrossQueueType myFunc1(int f_lim);
for (int i = 0; i < f_lim; ++i)
myFunc1.push_back('{i,i});
endfunction
bins one = myFunc1(cg_lim);
bins two = myFunc2(cg_lim);
function CrossQueueType myFunc2(logic [31:0] f_lim);
for (logic [31:0] i = 0; i < f_lim; ++i)
myFunc2.push_back('{2*i,2*i});
endfunction
}
endgroup
cg cg_inst = new(3);//每一个例化的时候再指定参数;
endmodule
结果如下:
cg_inst.aXb.one = <0.0> , <1.1>,<2.2>
cg_inst.aXb.two = <0.0>,<2.2>,<4.4>,
11. instance;
每个覆盖率例化的时候,是所有的合在一起收集,还是每个例化的地方,单独收集对应的覆盖率;
每个覆盖率单独例化的时候,可以指定最终呈现的名字;
covergroup g1 (int w, string instComment) @(posedge clk) ;
// track coverage information for each instance of g1 in addition
// to the cumulative coverage information for covergroup type g1
option.per_instance = 1;
// comment for each instance of this covergroup
option.comment = instComment;
12. 一些基本的选项,通常不使用;
//auto_bin_max, cross_auto_bin_max, goal, weight等等;
//参考如下:
(221条消息) [SV]SystemVerilog Coverage Options用法總結及案例_元直数字电路验证的博客-CSDN博客_coveragegroup option
也可以参考table 19-2;
13. 设置采样时刻;
一般来讲,是不指定采样时刻,然后再rm中比对通过后,手动sample, 可以保证采集数据的合理性和正确性;
也可以指定拍拍采集;covergroup g1 (int w, string instComment) @(posedge clk) ;
14. 数据边界描述;
[ $ : value ] => The set of values less than or equal to value
[ value : $ ] => The set of values greater or equal to value