PCIe 7.0定稿,最快2025下半年正式发布

作为业界广泛采用的高速串行点对点互联标准,PCIe自诞生以来历经多次迭代升级,现已成为CPU、GPU、FPGA、SSD等计算设备间不可或缺的互连桥梁。PCIe 7.0标准更是将数据传输速率提升至令人惊叹的32 GB/s(每通道)。

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PCI-SIG在2022年6月的美国开发者大会(US DevCon)上宣布了PCI Express 7.0规范的持续进展。2023年6月发布版本0.3,2024年4月份发布0.5版本。最新进展,PCIe 7.0 ver0.9版本已经开放,算是Final Draft了,不出意外,正式版本SPEC规范也将在2025年内部发布。

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尽管PCIe 7.0规范的最终版本预期将在2025年内面世,但由于研发、测试及制造过程中遇到的各种障碍,实际产品可能需要更长时间才能广泛普及。

PCIe 7.0 的关键特性目标
  • 带宽翻倍:

    • PCIe 7.0旨在将PCIe 6.0的传输速率(64 GT/s)提升一倍至128 GT/s的原始比特率,并通过x16配置提供高达512 GB/s的双向传输速度。这代表了数据吞吐量的一次重大飞跃,对于需要处理大量数据的应用至关重要。

  • 采用PAM4信号技术:

    • 继续使用并优化自PCIe 6.0引入的Pulse Amplitude Modulation with 4 levels (PAM4)信号技术,该技术允许每个时钟周期编码两个数据位,从而有效地提高了数据传输效率。

  • 关注通道参数和可达性:

    • 在设计中注重物理层的通道性能,确保信号在更长距离上的完整性,这对于数据中心内部的互联尤其重要。

  • 持续提供低延迟和高可靠性:

    • 确保数据传输不仅速度快,而且延迟极低、可靠性极高,这对实时应用如人工智能/机器学习(AI/ML)和云计算等非常重要。

  • 提高能效:

    • 随着设备性能的增强,能效问题变得越来越关键。PCIe 7.0致力于减少能源消耗,使数据中心和其他高性能计算环境更加环保和经济。

  • 保持向后兼容性:

    • 尽管引入了许多新技术,但PCIe 7.0仍然支持所有先前版本的PCIe技术,这意味着现有硬件投资可以得到保护,同时也能平滑过渡到新一代标准。

扩展阅读:

OBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 1.2. PCI EXPRESS LINK......................................................................................................... 39 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 1.3.1. Root Complex........................................................................................................ 41 1.3.2. Endpoints .............................................................................................................. 42 1.3.3. Switch.................................................................................................................... 45 1.3.4. Root Complex Event Collector.............................................................................. 46 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 46 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 47 1.5.1. Transaction Layer................................................................................................. 48 1.5.2. Data Link Layer .................................................................................................... 48 1.5.3. Physical Layer ...................................................................................................... 49 1.5.4. Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 53 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54 2.1.2. Packet Format Overview ...................................................................................... 56 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 58 2.2.1. Common Packet Header Fields ............................................................................ 58 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.3. TLP Digest Rules .................................................................................................. 65 2.2.4. Routing and Addressing Rules .............................................................................. 65 2.2.5. First/Last DW Byte Enables Rules........................................................................ 69 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules......................................................................................... 83 2.2.9. Completion Rules.................................................................................................. 97 2.2.10. TLP Prefix Rules ................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 104
Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.
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