DFT Compiler极简示例1

Test Protocol Example 1

电路结构

RTL

module tcrm (in1, in2, in3, clk, cdn, out1, out2);
input in1, in2, in3, clk, cdn;
output out1, out2;
reg U1, U2;
wire gated_clk;
always @(posedge clk or negedge cdn) begin
if (!cdn) U1 <= 1’b0;
else U1 <= in1;
end
assign gated_clk = clk & in3;
always @(posedge gated_clk or negedge cdn) begin
if (!cdn) U2 <= 1’b0;
else U2 <= in2;
end
assign out1 = U1;
assign out2 = U2;
endmodule

脚本

set_app_var search_path “…/ref …/ref/db ./rtl ./”
set_app_var target_library “sc_max.db”
set_app_var link_library “* sc_max.db dw_foundation.sldb”
set synthetic_library {dw_foundation.sldb}

set hdlin_enable_rtldrc_info true;
read_verilog rtl/tcrm.v
current_design tcrm
link
create_clock -name clk [get_ports clk] -period 100
compile -scan
write -format ddc -hierarchy -output results/tcrm.scan.ddc
write -format verilog -hierarchy -output results/tcrm.scan.no_protocol.vg
set_dft_signal -view existing_dft -type ScanClock -timing [list 45 55 ] -port clk
set_dft_signal -view existing_dft -type Reset -active_state 0 -port cdn
set_dft_signal -view existing_dft -type Constant -active_state 1 -port in3
create_test_protocol
write_test_protocol -output first.spf
write -format verilog -hierarchy -output results/tcrm.scan.protocol.vg

结果

（1）如果不定义in3为常量

dft_drc报告

Begin Pre-DFT violations...
 Warning: Clock input CP of DFF U2_reg not active when clocks are set on. (D9-1)
Pre-DFT violations completed...

（2）没有建立test协议之前，SI/SE是不知道如何连接的。

module tcrm ( in1, in2, in3, clk, cdn, out1, out2 );
  input in1, in2, in3, clk, cdn;
  output out1, out2;
  wire   gated_clk;
  sdcrq1 U1_reg ( .D(in1), .SD(1'b0), .SC(1'b0), .CP(clk), .CDN(cdn), .Q(out1)         );
  sdcrq1 U2_reg ( .D(in2), .SD(1'b0), .SC(1'b0), .CP(gated_clk), .CDN(cdn),         .Q(out2) );
  an02d1 U5 ( .A1(in3), .A2(clk), .Z(gated_clk) );
endmodule

（3）建立test协议之后，对SI/SE进行插入并连接

insert_dft

module tcrm ( in1, in2, in3, clk, cdn, out1, out2, test_si, test_se );
  input in1, in2, in3, clk, cdn, test_si, test_se;
  output out1, out2;
  wire   gated_clk;

  sdcrq1 U1_reg ( .D(in1), .SD(test_si), .SC(test_se), .CP(clk), .CDN(cdn), 
        .Q(out1) );
  sdcrq1 U2_reg ( .D(in2), .SD(out1), .SC(test_se), .CP(gated_clk), .CDN(cdn), 
        .Q(out2) );
  an02d1 U5 ( .A1(in3), .A2(clk), .Z(gated_clk) );
endmodule

（4）report_scan_path -view existing_dft

AS BUILT BY insert_dft
========================================
Scan_path    Len   ScanDataIn  ScanDataOut ScanEnable  MasterClock SlaveClock
-----------  ----- ----------- ----------- ----------- ----------- -----------
I 1          2     test_si     out2        test_se     clk         -

（5）report_scan_configuration

dc_shell> report_scan_configuration 
 
****************************************
Report : Scan configuration
Design : tcrm
Version: O-2018.06-SP1
Date   : Mon Sep 12 10:56:52 2022
****************************************

========================================
TEST MODE: all_dft
VIEW     : Specification
========================================
Chain count:                           Undefined
Scan Style:                            Multiplexed flip-flop
Maximum scan chain length:             Undefined
Exact scan chain length:               Undefined
Physical Partitioning:                 Horizontal
Replace:                               True
Preserve multibit segments:            False
Clock mixing:                          No mix
Internal clocks:                       none
Retiming Flops:                        none
Add lockup:                            True
Lockup type:                           latch
Insert terminal lockup:                False
Create dedicated scan out ports:       False
Shared scan in:                        0
Bidirectional mode:                    No bidirectional type
Internal Clock Mixing:                 False
Test Clocks by System Clocks:          False
Hierarchical Isolation:                False
Multiple Scan Enable:                  Disable
Pipeline Scan Enable:                  Disable
Voltage Mixing:                        False
Identify Shift Register:               False
Power Domain Mixing:                   False
Reuse MV Isolation Cells:              True
Multi LSSD:                            Disable

（6）report_dft_configuration

DFT Structures                         Status
--------------                         --------
Scan:                                  Enable
Fix Sets:                              Disable
Fix Resets:                            Disable
Fix Clocks:                            Disable
Fix Busses:                            Enable
Fix Bdirectional Ports:                Enable
Fix X Propagation:                     Disable
Control Points:                        Disable
Observe Points:                        Disable
Test Points:                           Disable
Testability:                           Disable
Logic BIST:                            Disable
Wrapper:                               Disable
Boundary scan:                         Disable
Scan Compression:                      Disable
Streaming Compression:                 Disable
Core Integration:                      Disable
Power Control:                         Disable
Pipeline Scan Data:                    Disable
Clock Controller:                      Disable
ConnectClockGating:                    Enable
Mode Decoding Style:                   Binary
IEEE 1500 control:                     Disable