使用SPI口配置的VERILOG代码

module sft24 (
input clk,wr,rst,
input [23:0]u24,
output reg ready,mosi,sck,csn
);

reg [7:0]cntr ;
reg [15:0] d  = 0 ;
reg [7:0] st,str ;
always @(posedge clk )str<=st ;
always @(posedge clk )  if (st!=str)  d<=0; else d<=d+1;
wire move = d >= 200 ;
reg [23:0] r24 ; 
always @*  ready = st==10 && wr ==0;
always @ (posedge clk)
case (st)
10: if (wr)  r24<=u24; 
20 : r24[23:0] <= {r24[22:0],1'b0};
endcase 
always @* mosi = r24[23];
always @(posedge clk )if (rst)st<=0; else 
case (st)
0: st<=10;
10:if(wr) st <= 15 ; 
15: st <= 16 ; 
16: if ( move ) st<= 17 ;  ///csn=0;
17: if ( move ) st<= 18 ; // sck=0;
18: if ( move ) st<= 19 ; //sck=1; only here sck=1
19: if ( cntr==23 ) st<=30;else st<=20;
20: st<=21 ;  //cntr++ , r24<<=1;
21: if ( move ) st<=17 ;
30: if ( move ) st<= 31 ;  
31: if ( move ) st<= 32 ;//csn=1
32: if ( move ) st<= 33 ;//csn=1
33: st<=10;
default st<=0; 
endcase 

always @(posedge clk)  if (rst)  cntr<=0; else if (st==15)cntr<=0; else if (st==20) cntr<=cntr+1;
always @(posedge clk)  sck <= st==18 ; 
always @(posedge clk) case (st)0:csn<=1; 16:csn<=0;31:csn<=1;endcase  
 
        
endmodule 

module CFG_ADF4001(
input clk , rst , start ,
output sck,csn,mosi,
output busy  
); 

localparam N=10;
localparam R=40;  
localparam  A_VDD   =    3 ;
localparam DGND     =  7 ; 
localparam LOCK_OUT     =  1 ; 

localparam MUX_OUT_SEL =  LOCK_OUT  ;  
 
localparam r0 =  (R<<2) | 0  ;
localparam r1 =  (N<<8) | 1  ;
localparam r2 = 24'h7882 |  MUX_OUT_SEL << 4  ;
localparam r3 = 24'h7883 |  MUX_OUT_SEL << 4  ; 
 
wire ready ;
reg [7:0]  st ; 
  
localparam r4 = r0 ; // R<<2 | 0  ;
localparam r5 = r1 ; //N<<2 | 1  ;
localparam r6 = r2 ; //24'h7882 |  16  ;
localparam r7 = r3 ; // 24'h7883 |  16 ; 

 
always @ (posedge clk )  if (rst )  st<=0; else case (st) 
0 : st <=10;
10: if (start ) st <= 20 ; 

20: if (ready)  st <= 21 ; 21 : st<=22;//wr<=1;
22: if (ready)  st <= 23 ; 23 : st<=24;//wr <=1 
24: if (ready)  st <= 25 ; 25 : st<=26;//wr <=1 
26: if (ready)  st <= 27 ; 27 : st<=28;//wr <=1 

28: if (ready)  st <= 29 ; 29 : st<=30;//wr <=1 
30: if (ready)  st <= 31 ; 31 : st<=32;//wr <=1 
32: if (ready)  st <= 33 ; 33 : st<=34;//wr <=1 
34: if (ready)  st <= 35 ; 35 : st<=36;//wr <=1 

36: if (ready)  st <= 40 ;

40: st<= 0 ; 
default st<=0; 
endcase 

 
wire st_idle = (start ==0 ) &&  (st ==10 ) ;
assign busy = ~st_idle ;

reg wr ;always @ (posedge clk ) case (st)  21,23,25,27,29,31,33,35:wr<=1; default wr<=0; endcase 

reg [23:0] u24 ;
always @ (posedge clk ) case (st)  

21: u24 <= r0 ;
23: u24 <= r1 ;
25: u24 <= r2 ;
27: u24 <= r3 ; 

29: u24 <= r4 ; 
31: u24 <= r5 ; 
33: u24 <= r6 ; 
35: u24 <= r7 ;  

endcase 

  sft24  sft24 (
  .clk( clk  ) ,
  .wr( wr ) ,
  .rst( rst ) ,
  .u24(u24  ) ,
  .ready(ready  ) ,
  .mosi( mosi ) ,
  .sck(sck  ) ,
  .csn(csn  ) 
);

endmodule 

 
 
module por#(parameter HI_BIT=8)(
input clk ,rst,
output reg  por
);
reg [HI_BIT:0]  cntr ;
always@(posedge clk ) if (rst ) cntr <= 0; else if(cntr[HI_BIT]==0)  cntr<=cntr+1;
always@(posedge clk ) por<= ~cntr[HI_BIT] ;
endmodule 


module ADF4001(
input FPGA_CLK ,
output     PLL_CSN            ,
output     PLL_DIN            ,
input      PLL_LCKED          ,
output     PLL_SCK            ,
output reg     PLL_LED 
);
    wire busy ;
    reg [31:0] c ;
    wire clk = FPGA_CLK;
    wire of= c==400*1000*1000 ;
    always @ (posedge clk)   if ( of ) c<=0 ; else  c<=c+1 ;
   // always @ (posedge clk)  if (of) PLL_LED <= ~ PLL_LED ;   
    always @ (posedge clk)  PLL_LED <=  PLL_LCKED ;   
    wire por_rst  ;

 por  por (  .clk(FPGA_CLK) , .rst(1'B0), .por(por_rst ));
wire start = of ;///  &  ( ~ PLL_LCKED ) ;
 CFG_ADF4001  CFG_ADF4001 (
 .clk( FPGA_CLK) , 
 .rst( por_rst ) , 
 .start( start ) , 
 .sck( PLL_SCK ),
 .csn( PLL_CSN ),
 .mosi( PLL_DIN ),
 .busy ( busy ) 
 );
 
 
endmodule