interface.sv

interface fifoPorts #(parameter DSIZE=8);
    logic wclk;
    logic rclk;
    logic [DSIZE-1:0] rdata;
    logic wfull;
    logic rempty;
    logic [DSIZE-1:0] wdata;
    logic winc,wrst_n;
    logic rinc,rrst_n;

    logic full_pre;
    logic empty_pre;
    clocking wcb @(posedge wclk);
        output winc;
        output wdata;
        input wfull;
    endclocking:wcb

    clocking rcb @(posedge rclk);
         output rinc;
         input rdata;
         input rempty;
    endclocking:rcb

    modport TB(clocking wcb,clocking rcb,output wrst_n,rrst_n.wclk.rclk);
    modport DUT(output rdata,wfull,rempty,full_pre,empty_pre,
                input wclk,wdata,rclk,winc,wrst_n,rinc,rrst_n
    );
endinterface