HDLBits学习笔记（44~50)

HDLBits学习笔记（44~50)

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题目44 Exams/m2014 q4h

题干：Implement the following circuit:

题目大意：实现如下所示电路。

题目分析：assign连续赋值。

答案：

module top_module (
    input in,
    output out);
	assign out = in;
endmodul

题目45 Exams/m2014 q4i

题干：Implement the following circuit:

题目分析：out接地输出恒为零，用连续赋值语句。

答案：

module top_module (
    output out);
	assign out = 1'b0;
endmodule

题目46 Exams/m2014 q4e

题干：Implement the following circuit:

题目分析：输入输出通过或非门连接输出out，组合逻辑电路使用连续赋值语句。

答案：

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~(in1|in2);
endmodule

题目47 Exams/m2014 q4f

题干：Implement the following circuit:
题目分析：输入in1与in2的非通过与门与out相连。组合逻辑电路用连续赋值语句。

答案：

module top_module (
    input in1,
    input in2,
    output out);
    assign out = (in1)&(~in2);
endmodule

题目48 Exams/m2014 q4g

题干：Implement the following circuit:

题目分析：输入in1 in2通过异或非门连接，其输出值与输入值in3通过异或门，与out相连。

答案：

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    assign out = ~((in1)^(in2))^(in3);
endmodule

题目49 Gates

题干：Build a combinational circuit with two inputs, a and b.There are 7 outputs, each with a logic gate driving it:

out_and: a and b
out_or: a or b
out_xor: a xor b
out_nand: a nand b
out_nor: a nor b
out_xnor: a xnor b
out_anotb: a and-not b

题目大意：构建一个两个输入a,b七个输出组合逻辑电路。

题目分析：按照要去分别用assign去赋值。

答案：

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a&b;
    assign out_or  = a|b;
    assign out_xor = a^b;
    assign out_nand= ~out_and;
    assign out_nor = ~out_or;
    assign out_xnor= ~out_xor;
    assign out_anotb=  a&(~b);
endmodule

题目50 7420

题干：The 7420 is a chip with two 4-input NAND gates.
Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.

题目大意：按图完成7420芯片的电路搭建。

题目分析：两个四输入与非门。使用连续赋值语句完成。

答案：

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = ~(p1a&p1b&p1c&p1d);
    assign p2y = ~(p2a&p2b&p2c&p2d);
endmodule