HDLBits学习笔记（99~106)

HDLBits学习笔记（99~106)

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题目99 Count15

题干：Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

题目大意：构建一个4比特的二进制计数器，计数范围从0到15，reset为同步复位并把CNT清空。

题目分析：因为15是4位二进制数的最大的数，在计数就会溢出的变为0。

答案：

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

 	always@(posedge clk)begin
         if(reset)begin
             q <=  4'b0;
         end
         else
            q <= q + 1'b1;
     end

endmodule

题目100 Count10

题干：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

题目大意：构建一个十位计数器从0计数到9，同步复位高电平有效变，CNT记录为0。

题目分析：相较于上一题，本题应多加一个判断条件为计数的第十次也要清零，可以理解为当前计数为9并且下一次计数的到来时清零。

答案：

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

 	always@(posedge clk)begin
         if(reset)begin
             q <=  4'b0;
         end
         else if(q == 4'd9)begin
             q <=  4'b0;
         end
         else begin
            q <= q + 1'b1;             
         end
     end

endmodule

题目101 Count1to10

题干：Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

题目大意：构建一个十位计数器从1计数到10，同步复位高电平有效变，CNT记录为1。

题目分析：本题相较与上一题相当于计数范围平移一个单位，长度不变，操作思路相同。

答案：

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

 	always@(posedge clk)begin
         if(reset)begin
             q <=  4'b1;
         end
         else if(q == 4'd10)begin
             q <=  4'b1;
         end
         else begin
            q <= q + 1'b1;             
         end
     end

endmodule

题目102 Countslow

题干：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

题目大意：同样的十位计数器，但只有在slowena为高时才在clk到来时计数。

答案：

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
 	always@(posedge clk)begin
         if(reset)begin
             q <=  4'b0;
         end
         else if(slowena)begin
             if(q == 4'd9)begin
                q <= 1'b0;
             end
             else begin
                q <= q + 1'b1;                  
             end
         end
         else begin
            q <= q;
         end
     end
endmodule

题目103 Exams/ece241 2014 q7a

题干：Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1
Enable Set high for the counter to run
Clk Positive edge-triggered clock input
Q[3:0] The output of the counter
c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
logic gates
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter’s enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

题目大意：使用题目中所给的模块count4，完成一个从1~12的计数器，其中，reset为1时将计数器变为1，enable为1时计数器开始运转，clk高电平触发计数。其中c_enable，c_load，c_d[3:0]都为count4模块的信号线，用于数据的验证。

题目分析：对题目所给的count4模块参数进行分析。c_enable为计数器使能信号，c_load为计数器重装载信号，c_d为计数器初值。

答案：

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //

	assign c_enable = enable;
    assign c_load   = reset | (Q == 4'd12 & enable);
    assign c_d      = 4'd1;
    
    count4 the_counter 
    (
        .clk		(clk),
        .enable	(c_enable), 
        .load		(c_load), 
        .d		(c_d),
        .Q(Q)
    );

endmodule

题目104 Exams/ece241 2014 q7b

题干：From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);

题目大意：把1000HZ的信号进行分频，借用题目所给的BCD计数器分成100HZ 10HZ 和1HZ，然后输出1HZ的信号和3路使能信号。

题目分析：主要是对BCD计数器模块进行例化，以达到输出1HZ信号的目的。

答案：

module top_module (
   input clk,
   input reset,
   output OneHertz,
   output [2:0] c_enable
); //
   assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};
   assign OneHertz = {q2 == 4'd9 && q1 == 4'd9 && q0 == 4'd9};
   
   bcdcount counter0 (clk, reset, c_enable[0], q0);
   bcdcount counter1 (clk, reset, c_enable[1], q1);
   bcdcount counter2 (clk, reset, c_enable[2], q2);

endmodule

题目105 Countbcd

题干：Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.

题目大意：构建一个4位BCD(二进制编码十进制)计数器。每个十进制数字使用4位进行编码：Q[3：0]为个位，Q[7：4]为十位，依此类推。对于ena[3：1]，还会输出一个使能信号，指示高位三位中的每一位何时应递增。

答案：

module top_module (
   input clk,
   input reset,   // Synchronous active-high reset
   output [3:1] ena,
   output [15:0] q);

   reg [3:0] ones        ;
   reg [3:0] tens        ;
   reg [3:0] hundreds    ;
   reg [3:0] thousands   ;

   wire enaa ;

   assign q = {thousands, hundreds, tens, ones};
   assign ena[1] = (ones == 4'd9)?(1'b1):(1'b0);
   assign ena[2] = (ones == 4'd9 && tens == 4'd9)?(1'b1):(1'b0);
   assign ena[3] = (ones == 4'd9 && tens == 4'd9 && hundreds == 4'd9)?(1'b1):(1'b0);
   assign enaa   = (ones == 4'd9 && tens == 4'd9 && hundreds == 4'd9 && thousands == 4'd9)?(1'b1):(1'b0);

   always @(posedge clk ) begin
      if(reset)begin
         ones     <= 1'b0;
         tens     <= 1'b0;
         hundreds <= 1'b0;
         thousands<= 1'b0; 
      end
      else begin
         ones <= ones + 1'b1;
         if(ena[1])begin
            tens <= tens + 1'b1;
            ones <= 1'b0;
         end
         if(ena[2])begin
            hundreds <= hundreds + 1'b1;
            tens     <= 1'b0;
         end
         if(ena[3])begin
            thousands <= thousands + 1'b1;
            hundreds  <= 1'b0;
         end
         if(enaa)begin
            thousands <= 1'b0;
         end
      end 
   end

endmodule

题目106 Count clock

题干：Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour

题目大意：创建一组适合用作12小时时钟的计数器(带有AM/PM指示器)。您的计数器由快速运行的CLK计时，每当您的时钟应该递增(即每秒一次)时，ENA上就会有一个脉冲。
重置将时钟重置为上午12：00。AM为0，PM为1。HH、MM和SS是两个BCD(二进制编码的十进制)数字，分别表示小时(01-12)、分钟(00-59)和秒(00-59)。重置的优先级高于启用，即使未启用也可能发生。
下面的时序图显示了从上午11：59：59到下午12：00：00的翻转行为以及同步重置和启用行为。

题目分析：注意时钟的数采用BCD计数器方式。
答案：

module top_module (
   input clk,
   input reset,
   input ena,
   output pm,
   output [7:0] hh,
   output [7:0] mm,
   output [7:0] ss); 

   wire [2:0] enaa ;
   wire [2:0] enax ;
   wire enpm ;

   reg [3:0] ss_ones;
   reg [3:0] ss_tens;

   reg [3:0] mm_ones;
   reg [3:0] mm_tens;

   reg [3:0] hh_ones;
   reg [3:0] hh_tens;

   assign enaa[0] = (ss == 8'h59)?(1'b1):(1'b0);
   assign enaa[1] = (ss == 8'h59 && mm == 8'h59)?(1'b1):(1'b0);
   assign enaa[2] = (ss == 8'h59 && mm == 8'h59 && hh == 8'h12)?(1'b1):(1'b0);

   assign enax[0] = (ss_ones == 4'h09)?(1'b1):(1'b0);
   assign enax[1] = (mm_ones == 4'h09)?(1'b1):(1'b0);
   assign enax[2] = (hh_ones == 4'h09)?(1'b1):(1'b0);
   assign enpm = (ss == 8'h59 && mm == 8'h59 && hh == 8'h11)?(1'b1):(1'b0);

   assign ss = {ss_tens, ss_ones};
   assign mm = {mm_tens, mm_ones};
   assign hh = {hh_tens, hh_ones};

   always @(posedge clk ) begin
      if(reset)begin
         ss_ones <= 1'b0;
         ss_tens <= 1'b0;
         mm_ones <= 1'b0;
         mm_tens <= 1'b0;
         hh_ones <= 4'd2;
         hh_tens <= 4'd1;
         pm   <= 1'b0;
      end
      else begin
         if(ena)begin
            ss_ones <= ss_ones + 1'b1;
            if(enax[0])begin
               ss_ones <= 4'h00;
               ss_tens <= ss_tens + 1'b1;
            end
         end
         if(enaa[0])begin
            ss_tens <= 1'b0;
            mm_ones <= mm_ones + 1'b1;
            if(enax[1])begin
               mm_ones <= 4'h00;
               mm_tens <= mm_tens + 1'b1;
            end
         end
         if(enaa[1])begin
            mm_tens <= 1'b0;
            hh_ones <= hh_ones + 1'b1;
            if(enax[2])begin
               hh_ones <= 4'h00;
               hh_tens <= hh_tens + 1'b1;
            end
         end
         if(enaa[2])begin
            hh_tens <= 1'b0;
            hh_ones <= 1'b1;
         end
         if(enpm)begin
            pm <= ~pm;
         end
      end
   end
endmodule