HDLBits学习笔记（116~118)

HDLBits学习笔记（116~118)

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题目116 Rule90

题干：
Rule 90 is a one-dimensional cellular automaton with interesting properties.
The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell’s two current neighbours. A more verbose way of expressing this rule is the following table, where a cell’s next state is a function of itself and its two neighbours:
In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off)

题目大意：建立一个512元胞的电路，每一个元素的下一个状态都是其两侧元素的异或结构，假定q[-1] 和 q[512]都是零。

答案：

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
	always @(posedge clk ) begin
        if(load)begin
            q <= data; 
        end
        else begin
            q <= (q<<1)^(q>>1);
        end
    end
endmodule

题目117 Rule110

题干：Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete).

There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:

题目大意：卡诺图化简，假定q[-1] 和 q[512]都是零。卡诺图化简后得到 Center^Right + ~Left*Right。

答案：

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
	int i;
    always @(posedge clk ) begin
        if(load)
            q <= data;
        else begin
            q[0]        <=  q[0];
            q[511]      <=  (q[511] ^ q[510] )|| ( q[510] );
            for(i = 1; i<511;i=i+1)
                q[i] <= (q[i] ^ q[i - 1] )|| (!q[i+1] & q[i-1]); 
        end
    end
endmodule

题目118 Conwaylife

题干：The “game” is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:
0-1 neighbour: Cell becomes 0.
2 neighbours: Cell state does not change.
3 neighbours: Cell becomes 1.
4+ neighbours: Cell becomes 0.

题目大意：

这个游戏是针对无限网格而设计的。在本电路中，我们将使用16x16栅格。为了让事情更有趣，我们将使用一个16x16的环形，其中的两边绕到网格的另一边。例如，角单元(0，0)有8个相邻单元：(15，1)、(15，0)、(15，15)、(0，1)、(0，15)、(1，1)、(1，0)和(1，15)。16x16格网由长度为256的矢量表示，其中每行16个像元由一个子矢量表示：Q[15：0]表示第0行，Q[31：16]表示第1行，依此类推(此工具接受SystemVerilog，因此如果愿意，您可以使用2D矢量。
0-1：小区变为0。
2：小区状态不变。
3：单元格变为1。
4：单元格变为0。

题目分析：通过对每一个元素的邻域的查找，加和计算出1的个数，然后对下一个状态进行判断，主要问题是要考虑，边源元素的邻域。

答案：

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    
    wire [4:0] num[255:0];    
    generate
        genvar i;
        for(i=0;i<256;i=i+1)begin:add
           find(
                    .data	(q),
                    .num	(i),      
               		.q		(num[i])
                );
            always@(posedge clk)begin
                if(load)
                    q[i]<=data[i];
                else case(num[i])
                    4'd0:q[i]<=1'b0;
					4'd1:q[i]<=1'b0;
                    4'd2:q[i]<=q[i]^1'b0;
                    4'd3:q[i]<=1'b1;
                    4'd4:q[i]<=1'b0;
                    default:q[i]<=1'b0;
                endcase
            end
        end
    endgenerate

endmodule

module find(
    input wire [255:0] data,
    input wire [7:0] num,
    output wire [4:0]q
);
    wire[4:0] hang_cnt,lie_cnt,hang_cnt_s,hang_cnt_x,lie_cnt_s,lie_cnt_x;
    wire [7:0] hang_xi;
    wire [7:0] loca_1;
    wire [7:0] loca_2;
    wire [7:0] loca_3;
    wire [7:0] loca_4;
    wire [7:0] loca_5;
    wire [7:0] loca_6;
    wire [7:0] loca_7;
    wire [7:0] loca_8;
    
    assign hang_cnt = num>>4;
    assign lie_cnt = num%16;
    assign hang_xi = hang_cnt<<4;
    
//右邻     
    assign loca_1=(lie_cnt == 5'd15)?(num-15):(num+1);
//左邻
    assign loca_2=(lie_cnt == 5'd0)?(num+15):(num-1); 
 //上邻 
    assign loca_3=(hang_cnt == 5'd0)?(240+lie_cnt):(num-16); 
 //下邻
    assign loca_4=(hang_cnt == 5'd15)?(lie_cnt):(num+16);  
    
   
    assign hang_cnt_s = loca_3>>4;
    assign hang_cnt_x = loca_4>>4;
    
    assign lie_cnt_s = loca_3%16;
    assign lie_cnt_x = loca_4%16;
    
 //左上
    assign loca_5=(lie_cnt_s == 5'd0)?(loca_3+15):(loca_3-1);
 //右上
    assign loca_6=(lie_cnt_s == 5'd15)?(loca_3-15):(loca_3+1);
 //左下
    assign loca_7=(lie_cnt_x == 5'd0)?(loca_4+15):(loca_4-1);
 //右下
    assign loca_8=(lie_cnt_x == 5'd15)?(loca_4-15):(loca_4+1);
    
    assign q=data[loca_1]+data[loca_2]+data[loca_3]+data[loca_4]+data[loca_5]+data[loca_6]+data[loca_7]+data[loca_8];
    
endmodule