Error (10200)：错误的另一种可能

always @ (posedge clk or negedge rst_n/* or negedge add or negedge count_en*/) begin
    if (!rst_n)begin
        data  <= 6'b0;
        point <=6'b000000;
        en    <= 1'b0;
        sign  <= 1'b0;
    end 
    else if(count_en) begin
        point <= 6'b000000;             //不显示小数点
        en    <= 1'b1;                  //打开数码管使能信号
        sign  <= 1'b0;                  //不显示负号
        if (flag ) begin                 //显示数值每隔0.1s累加一次
            if(data < 6'd59)begin 
                data <= data +1'b1;
					 add_out <= 1'b0;
				end
            else begin
                data <= 6'b0;
					 add_out <= 1'b1;
				end 
        end 
    end
	  if(add)
		data <= data +1'b1;
end 

 错误代码：Error (10200): Verilog HDL Conditional Statement error at count.v(90)（即倒数第三行if（add）处）: cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

错误代码提示不能将条件中的操作数与always构造的封闭事件控件中的相应边匹配 ，可以理解为此处逻辑并没有形成闭环，可能是一个always里面出现了两个逻辑环导致报错，在if前加入else可以解决报错