学了一段时间的Verilog总结二

本人将根据教材《Verilog数字系统教程》-----（夏宇闻）学习总结
本文章为实例主题（二）

程序总结二

七人表决器

code

module vote(in,result);
input[6:0] in;
output result;
wire[2:0] count;
    assign count = in[0] + in[1] + in[2] + in[3] + in[4] + in[5] + in[6];
    assign result = (count >= 4) ? 1 : 0;
endmodule

testbench

`timescale 1 ps/ 1 ps
module vote_t();
reg [6:0] in;                                              
wire result;
vote i1 (
   
	.in(in),
	.result(result)
);
initial                                                
begin                                                  
#100  in=7'b0000000;                                       
#100  in=7'b0000001; 
#100  in=7'b0000011; 
#100  in=7'b0000111; 
#100  in=7'b0001111; 
#100  in=7'b0011111; 
#100  in=7'b0111111; 
#100  in=7'b1111111; 
#500 $stop; 
end                                                                                                                                                    
endmodule

八位全加器

code

module fulladd8(s, cout, a, b, cin);
	output [7 : 0] s;
	output cout;
	input [7 : 0] a, b;
	input cin;
	wire [6 : 0] carry;
	fulladder m0(s[0], carry[0], a[0], b[0], cin);
	fulladder m1(s[1], carry[1], a[1], b[1], carry[0]);
	fulladder m2(s[2], carry[2], a[2], b[2], carry[1]);
	fulladder m3(s[3], carry[3], a[3], b[3], carry[2]);
	fulladder m4(s[4], carry[4], a[4], b[4], carry[3]);
	fulladder m5(s[5], carry[5], a[5], b[5], carry[4]);
	fulladder m6(s[6], carry[6], a[6], b[6], carry[5]);
	fulladder m7(s[7], cout, a[7], b[7], carry[6]);
endmodule
module fulladder(s, cout, a, b, cin);
	output s, cout;
	input a, b, cin;
	assign s = a ^ b ^ cin;
	assign cout = a & b | a & cin | b & cin;
endmodule

testbench

`timescale 1ns/1ns
module fulladd8_t(s, cout);
	output [7 : 0] s;
	output cout;
	reg [7 : 0] a, b;
	reg cin;
	initial
	begin
		#100 a = 8'b0000_0000; b = 8'b0000_0000; cin = 1'b0; 
		#100 a = 8'b0000_0001; b = 8'b0000_0001; cin = 1'b1; 
		#100 a = 8'b0010_0000; b = 8'b0010_0011; cin = 1'b1; 
		#100 a = 8'b1111_1100; b = 8'b0000_0011; cin = 1'b0; 
		#100 a = 8'b1111_1100; b = 8'b0000_0011; cin = 1'b1; 
		#100 a = 8'b1111_1100; b = 8'b0000_1000; cin = 1'b0; 
		#500 $stop;
	end
	fulladd8 m0(.s(s), .cout(cout), .a(a), .b(b), .cin(cin));
endmodule

奇校验收发电路

Code

module oddsend(datain,dataout);
input [7:0] datain;
output [8:0] dataout;
//assign dataout = datain[0] ^ datain[1] ^ datain[2] ^ datain[3] ^ datain[4] ^ datain[5] ^ datain[6]^ datain[7];
assign dataout[8] = ^ datain;
endmodule

testbench

`timescale 1 ps/ 1 ps
module oddsend_t();
reg [7:0] datain;                                              
wire [8:0]  dataout;                         
oddsend i1 (
	.datain(datain),
	.dataout(dataout)
);                                                
/*initial
	begin
		#100 datain = 8'b0000_0000; 
		#100 datain = 8'b0000_0001; 
		#100 datain = 8'b0000_0011; 
		#100 datain = 8'b0000_0111; 
		#100 datain = 8'b0000_1111; 
		#100 datain = 8'b0001_1111; 
		#100 datain = 8'b0011_1111; 
		#100 datain = 8'b0111_1111; 
		#100 datain = 8'b1111_1111; 		
		#500 $stop;
	end */
initial begin
		datain = 8'b0000_0000;	
	   end
	always #100 	datain = datain + 8'd1;
endmodule

八分频器

Code

module divfreu8(clkin,clkout);
input clkin;
output clkout;
parameter n=8;
integer count;
reg clkout;
always @(posedge clkin)
	begin 
	if (count<n-1) count<=count + 1;
	else count <=0;
	end 	
always @(count)
	begin 
	if (count<n/2) clkout<=1'b1;
	else clkout <= 1'b0;
	end 
endmodule

testbench

`timescale 1 ps/ 1 ps
`define cycle 50
module divfreu8_t();
reg clkin;                                              
wire clkout;
reg reset;                   
divfreu8 i1 (   
	.clkin(clkin),
	.clkout(clkout)
);
always #`cycle clkin = ~ clkin;
initial                                                
begin
		clkin = 0;
		reset = 1;
		#10 reset = 0;
		#110 reset = 1;
		#10000 $stop;                  
end                                                                                              
endmodule

移位寄存器

Code

module shift8(D,rst,clk,mode,Q);
input  D,clk,rst;
input[1:0] mode;
output [7:0] Q;
reg [7:0] Q;
always@(posedge clk)
begin
if (!rst )  Q = 8'b0000_0000;
else if(mode ==2'b00)  //00左移 01右移 10 循环移位 11清除
  begin 
  Q <= (Q <<1);
  Q [0] <= D ;
  end 
 else  if (mode ==2'b01)
 begin 
  Q <= (Q>>1);
  Q [7] <= D ;
 end  
 else if (mode ==2'b10)
	Q <= {Q[6:0],Q[7]};	
 else 
	 Q <= 8'b0000_0000;	 
end
endmodule

testbench

`timescale 1 ps/ 1 ps
module shift8_t();
reg D;
reg clk;
reg [1:0] mode;
reg rst;                                          
wire [7:0]  Q;                          
shift8 i1 (   
	.D(D),
	.Q(Q),
	.clk(clk),
	.mode(mode),
	.rst(rst)
);      
always 
begin 
#50 clk=~clk ;
end                                     
initial
begin 
mode = 2'b00;
clk =0;
rst = 0;
D = 0;
#100  rst = 1;D=0;
#100 D = 1;
#100 D = 0;
#200 D = 1;
#100 D = 0;
#100 D = 1;
#100 D = 0;
/*************/
mode = 2'b01;
clk =0;
rst = 0;
D = 0;
#50  rst = 1;D=0;
#100 D = 1;
#100 D = 0;
#200 D = 1;
#100 D = 0;
#100 D = 1;
#100 D = 0;
/****************/
mode = 2'b10;
clk =0;
rst = 0;
D = 0;
#50  rst = 1;D=0;
#100 D = 1;
#100 D = 0;
#200 D = 1;
#100 D = 0;
#100 D = 1;
#100 D = 0;
/************/
mode = 2'b11;
clk =0;
rst = 0;
D = 0;
#50  rst = 1;D=0;
#100 D = 1;
#100 D = 0;
#200 D = 1;
#100 D = 0;
#100 D = 1;
#100 D = 0;
#200 $stop;
end
endmodule

作者寄语

本文章为电路模板代码配测试代码。
本文章注释的部分为其他方法。
这些程序大同小异，理解为主即可。
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