接上一篇文章,DUT不变,下面是schematic
tb文件tinyalu_tb.sv
module top;
typedef enum bit[2:0] {no_op = 3'b000,
add_op = 3'b001,
and_op = 3'b010,
xor_op = 3'b011,
mul_op = 3'b100,
rst_op = 3'b111} operation_t;
byte unsigned A;
byte unsigned B;
bit clk;
bit reset_n;
wire [2:0] op;
bit start;
wire done;
wire [15:0] result;
operation_t op_set;
assign op = op_set;
tinyalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .result);
initial begin
clk = 0;
forever begin
#10;
clk = ~clk;
end
end
function operation_t get_op();
bit [2:0] op_choice;
op_choice = $random;
case (op_choice)
3'b000 : return no_op;
3'b001 : return add_op;
3'b010 : return and_op;
3'b011 : return xor_op;
3'b100 : return mul_op;
3'b101 : return no_op;
3'b110 : return rst_op;
3'b111 : return rst_op;
endcase // case (op_choice)
endfunction : get_op
function byte get_data();
bit [1:0] zero_ones;
zero_ones = $random;
if (zero_ones == 2'b00)
return 8'h00;
else if (zero_ones == 2'b11)
return 8'hFF;
else
return $random;
endfunction : get_data
initial begin : tester
reset_n = 1'b0;
@(negedge clk);
@(negedge clk);
reset_n = 1'b1;
start = 1'b0;
repeat (1000) begin
@(negedge clk);
op_set = get_op();
A = get_data();
B = get_data();
start = 1'b1;
case (op_set) // handle the start signal
no_op: begin
@(posedge clk);
start = 1'b0;
end
rst_op: begin
reset_n = 1'b0;
start = 1'b0;
@(negedge clk);
reset_n = 1'b1;
end
default: begin
wait(done);
start = 1'b0;
end
endcase // case (op_set)
end
$finish();
end : tester
initial begin
$fsdbDumpfile("tinyalu");
$fsdbDumpvars;
$vcdpluson;
end
endmodule : top
打开波形
收集覆盖率
双击进入未收集到的
枚举类型增加default_op,case语句修改3’b110 : return default_op;
typedef enum bit[2:0] {no_op = 3'b000,
add_op = 3'b001,
and_op = 3'b010,
xor_op = 3'b011,
mul_op = 3'b100,
default_op = 3'b110,
rst_op = 3'b111} operation_t;
function operation_t get_op();
bit [2:0] op_choice;
op_choice = $random;
case (op_choice)
3'b000 : return no_op;
3'b001 : return add_op;
3'b010 : return and_op;
3'b011 : return xor_op;
3'b100 : return mul_op;
3'b101 : return no_op;
3'b110 : return default_op;
3'b111 : return rst_op;
endcase // case (op_choice)
endfunction : get_op
重新make clean后,继续在sim文件下make comp run,dve打开覆盖率文件
dve -full64 -covdir simv.vdb&
覆盖率为100%