8.1 分频
// 8.1 分频
module fdiv8_1 (
input wire sys_clk ,
input wire sys_rst_n ,
output reg clk_out
);
reg [3:0] cnt1 ;
reg [3:0] cnt2 ;
// cnt1 ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt1 <= 4'd0 ;
end else begin
if(cnt2 != 4'd9) begin
if(cnt1 == 4'd7) begin
cnt1 <= 4'd0 ;
end else begin
cnt1 <= cnt1 + 4'd1 ;
end
end else begin
if(cnt1 == 4'd8) begin
cnt1 <= 4'd0 ;
end else begin
cnt1 <= cnt1 + 4'd1 ;
end
end
end
end
// cnt2 ;
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
cnt2 <= 4'd0 ;
end else begin
if(cnt2 != 4'd9) begin
if(cnt1 == 4'd7) begin
cnt2 <= cnt2 + 4'd1 ;
end else begin
cnt2 <= cnt2 ;
end
end else begin
if(cnt1 == 4'd8) begin
cnt2 <= 4'd0 ;
end else begin
cnt2 <= cnt2 ;
end
end
end
end
// clk_out
always @(posedge sys_clk or negedge sys_rst_n) begin
if(~sys_rst_n) begin
clk_out <= 1'b0 ;
end else begin
if(cnt2 != 4'd9) begin
if(cnt1 == 4'd7) begin
clk_out <= 1'b1 ;
end else begin
clk_out <= 1'b0 ;
end
end else begin
if(cnt1 == 4'd8) begin
clk_out <= 1'b1 ;
end else begin
clk_out <= 1'b0 ;
end
end
end
end
endmodule
`timescale 1ns/1ns
module test();
reg clkin ;
reg clr ;
wire clk_out ;
// Instantiation
fdiv8_1 fdiv8_1_insert(
.sys_clk ( clkin ) ,
.sys_rst_n ( clr ) ,
.clk_out ( clk_out )
);
parameter CYCLE = 20 ;
initial begin
clkin = 1'b1 ;
clr <= 1'b0 ;
#( CYCLE * 10 ) ;
clr <= 1'b1 ;
#( 210 ) ;
clr <= 1'b0 ;
#( 10 ) ;
#( CYCLE * 10 ) ;
clr <= 1'b1 ;
#( CYCLE * 1000 ) ;
$stop ;
end
always #( CYCLE / 2 ) clkin = ~clkin ;
endmodule