一大波HLS设计资料来了

最新推荐文章于 2024-06-14 17:09:40 发布

OpenFPGA

最新推荐文章于 2024-06-14 17:09:40 发布

阅读量707

点赞数

分类专栏： HLS 文章标签： nagios js webrtc 比特币 openstack

HLS 专栏收录该内容

19 篇文章

订阅专栏

手边的学习资料

安装Vivado HLS以后，既包含了20个designexample，50个code example:

step by step教程

ug871 是xilinx公开提供的HLS教程，包括十几个例子：

C Validation

Interface Synthesis

Arbitrary Precision Types

Design Analysis

Design Optimization

RTL Verification

Using HLS IP in IP Integrator

Using HLS IP in a Zynq Processor Design

Using HLS IP in System Generator for DSP

链接：https://pan.baidu.com/s/1K01CJ0KTwqXGk0lrBfIgrg

提取码：6jae

18个Xilinx专家讲解视频

包括讲座和演示

1、Getting Started with Vivado High-Level Synthesis

https://www.xilinx.com/video/hardware/getting-started-vivado-high-level-synthesis.html

2、Using Vivado HLS C, C++,System-C Block in System Generator

https://www.xilinx.com/video/hardware/vivado-hls-c-system-c-system-generator.html

3、Vivado High LevelSynthesis

Vivado High-Level Synthesis accelerates design implementation by enabling C, C++ and System C specifications to be directly targeted into Xilinx devices without the need to manually create RTL.

https://www.xilinx.com/video/hardware/vivado-high-level-synthesis.html

4、Vivado HLSIn-depth Technical Overview

Vivado HLS contributes to overall system power reduction, reduced bill of materials cost, increased system performance and accelerated design productivity. We’ll show you how to create a more efficient specification using C, C++, or SystemC.

https://www.xilinx.com/video/hardware/vivado-hls-in-depth-technical-overview.html

5、Leveraging OpenCV and High Level Synthesis with Vivado

Learn about the OpenCV libraries and typical applications, the advantages of Zynq-7000 AP SoC and implementing OpenCV design, how HLS and video libraries can be used in the process and a demonstration of an example design.

https://www.xilinx.com/video/hardware/leveraging-opencv-synthesis-vivado.html

6、Floating PointDesign with Vivado HLS

Learn how floating-point C code can be easily transformed into an RTL. This video explains the support provided inVivado HLS for floating-point design, including which operations and math functions are available for synthesis.

https://www.xilinx.com/video/hardware/floating-point-design-with-vivado-hls.html

7、Leveraging OpenCV and High Level Synthesis with Vivado

https://www.xilinx.com/video/hardware/leveraging-opencv-synthesis-vivado.html

8、Vivado HLSIn-depth Technical Overview

https://www.xilinx.com/video/hardware/vivado-hls-in-depth-technical-overview.html

9、Generating VivadoHLS Pcore for use in Xilinx Platform Studio

Learn how to generate a pcore IP block using Vivado HLS for use in Xilinx Platform Studio. This video explains everything you need to know about the Export RTL feature, including device& license support, the other available export formats and how to evaluate the Vivado HLS design by launching RTL synthesis from within Vivado HLS. This video ends with a summary of how the Vivado HLS IP can be imported into XilinxPlatform Studio as a pcore.

https://www.xilinx.com/video/hardware/vivado-hls-pcore-platform-studio.html

10、Getting Started with Vivado High-Level Synthesis

Learn how to use the GUI interface to create a Vivado HLS project, compile and execute your C, C++ or SystemCalgorithm, synthesize the C design to an RTL implementation, review the reports and understand the output file.

https://www.xilinx.com/video/hardware/getting-started-vivado-high-level-synthesis.html

11、Using the VivadoHLS Tcl Interface

Learn how to the Tcl command language to run Vivado HLS in batch mode and improve productivity. This video shows how anew Tcl batch script can easily be created from an existing Vivado HLS design.

https://www.xilinx.com/video/hardware/using-the-vivado-hls-tcl-interface.html

12、GeneratingVivado HLS block for use in System Generator for DSP

Learn how to generate a Vivado HLS IP block for use in the System Generator For DSP.

https://www.xilinx.com/video/hardware/vivado-hls-block-system-generator-dsp.html

13、Using Vivado HLSSW Libraries in your C, C++, System-C Code

Learn how to use the C libraries provided with Vivado HLS to both ease the design capture of video algorithms and create a productive methodology when designing with C math functions.

https://www.xilinx.com/video/hardware/vivado-hls-sw-libraries-in-your-c-system-c-code.html

14、Verifying yourVivado HLS Design

Learn how to verify your Vivado HLS design from C, C++ or SystemC through to the RTL implementation. Understand the important attributes of a good C/C++/SystemC testbench in enabling a highly-productive push-button verification flow from C to RTL.

https://www.xilinx.com/video/hardware/verifying-your-vivado-hls-design.html

15、Using Vivado HLSC, C++, System-C Based Pcores in XPS

Learn how to incorporate your Vivado HLSdesign as an IP block into both Xilinx Platform Studio and the SoftwareDevelopment Kit. See how a Vivado HLS design can be saved as pcore IP and learn how this IP can be easily incorporated into an embedded system using XilinxPlatform Studio. In addition, this video shows how software drivers are created for the IP and how these can be used to speed the software development in SDK, allowing systems to be built quickly.

https://www.xilinx.com/video/hardware/vivado-hls-c-system-c-pcores-in-xps.html

16、Vivado HighLevel Synthesis

Vivado High-Level Synthesis accelerates design implementation by enabling C, C++ and System C specifications to be directly targeted into Xilinx devices without the need to manually create RTL.

https://www.xilinx.com/video/hardware/vivado-high-level-synthesis.html

17、Packaging VivadoHLS IP for use from Vivado IP Catalog

Learn how to package your Vivado HLS IP fo ruse in the Vivado IP Catalog. This video explains everything you need to known about the Export RTL feature, including device & license support, the other available export formats and how to evaluate the Vivado HLS design by launchingRTL synthesis from within Vivado HLS. This video ends with a summary of how the Vivado HLS IP can be add to the Vivado IP Catalog.

https://www.xilinx.com/video/hardware/vivado-hls-ip-vivado-ip-catalog.html

不停更新的武林秘籍

https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html

www.xilinx.com/hls