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Digital Design 2020-21
VHDL
Coursework
1 Objectives
The objective of this assignment is to use VHDL to design and implement the processing required for
the control logic of a pedometer. The correctness of the design should be illustrated through
simulations.
2 Deliverables:
A report showing:
A completed design for a pedometer using VHDL and targeted to an Artix7 FPGA.
An explanation of the design decisions and testing methodologies.
A set of simulations showing the correct operation of the design.
3 Assignment Specification
A pedometer is a wearable device that detect footsteps automatically and, from this
information, can estimate distances travelled, speed etc. In a complete system, the input to
该课程作业旨在使用VHDL设计并实现一款步数计数器，模拟应用于计步器的控制逻辑。设计需在Artix7 FPGA上完成，并通过仿真验证正确性。设计包括步数显示、距离估算、平均步频和平均速度等功能，输入通过FPGA板上的按钮模拟，输出通过7段数码管反馈。报告需包含设计介绍、仿真结果、综合结果和结论，同时提交VHDL源代码。
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