堆栈verilog设计实现及仿真

堆栈顶层模块设计代码如下：

使用verilog设计实现堆栈的写入和读出功能

工程及仿真如下：

代码设计如下：

module stack(input wire clk, reset, push, pop, input wire [15:0] value_in, output wire [15:0] value_out, output wire full, empty);
wire is_7, is_7_reg, is_0, is_0_reg, write_push, write_pop, top_write_enable, carry_a, carry_s;
wire [2:0] top, inc, dec, inc_dec;
wire [15:0] d_care;
regr_1 reg1(clk, reset, is_7, is_7_reg);
//push
mux2 push_checker(push, 1’b0, is_7_reg, write_push);

regs_1 reg2(clk, reset, is_0, is_0_reg);
//pop
mux2 pop_checker(pop, 1'b0, is_0_reg, write_pop);

or2 top_reg_writer(write_pop,