ERROR:HDLCompilers:246-"lfsrtest.v" line 36 Reference to vector reg 'random_value' is not a legal net lvalue
ERROR:HDLCompilers:53-"lfsrtest.v" line 36 Illegal left hand side of continuous assign
修改:
module lfsr(
input clk,// 时钟输入信号
input reset,// 复位输入信号
output reg [7:0] random_value // 输出8位随机值);
reg [7:0] lfsr_reg;
always @(posedge clk or posedge reset) begin
if(reset) begin
lfsr_reg <=8'h1;// LFSR初始化
end else begin
lfsr_reg <={lfsr_reg[6:0], lfsr_reg[7]^ lfsr_reg[5]};// 生成随机数
end
end
always @(posedge clk or posedge reset) begin
if(reset) begin
random_value <=8'h1;// 重置时,random_value初始化
end else begin
random_value <= lfsr_reg;// 每个时钟周期更新random_value
end
end
endmodule