【AMBA总线三部曲】APB协议理解

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分类专栏：汽车芯片IC验证文章标签： arm开发

于 2023-12-05 16:49:53 首次发布

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本文详细介绍了AMBA 3 APB协议，包括概述、信号描述、操作状态和数据传输。APB协议适用于连接各种外围设备如I2C、SPI、UART。内容涵盖APB时钟、复位信号、地址、选择、使能、读写方向等关键信号的解释，并强调了正确理解和验证这些信号对于节省验证时间的重要性。

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APB Protocol

工作项目中，不论用到的VIP是APB/AHB/AXI?工作的第一步，首先要做的工作是确认接口上的时钟和复位是否正常；VIP interface上的时钟和复位是否都正常，然后进行下一步的工作。可以帮助验证人员节省80%的debug时间！

APB Protocol

1. 概述简介

2. Signal Descriptions

3. Operating States

4 Transfers

AMBA 3 APB Protocol Specification

1. 概述简介

• APB: Advanced Peripheral Bus ( 高级外设总线 )

• 应用场景：提供了一个低功耗接口，降低接口复杂性。

• 特性：

• 可工作在高频下

• 协议简单：无复杂的时序

• 控制逻辑简单

• 同步总线：总线上所有的 transaction （读写操作）都依赖于时钟的上升沿

• 一主多从：一般情况下， APB 挂在 AHB 总线系统下，通过 AHB-APB Bridge 将事务在 AHB 总线系统之间进行转化，此时 Bridge 即为 APB 的 master ，其他的外围设备均为 slave

可连接多种外围设备：I2C、SPI、UART

2. Signal Descriptions

PCLK Clock source Clock. The rising edge of PCLK times all transfers on the APB.

PRESETn System bus equivalent Reset. The APB reset signal is active LOW. This signal is normally connected directly to the system bus reset signal.

PADDR APB bridge Address. This is the APB address bus. It can be up to 32 bits wide and is driven by the peripheral bus bridge unit.

PSELx APB bridge Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. There is a PSELx signal for each slave.

PENABLE APB bridge Enable. This signal indicates the second and subsequent cycles of an APB transfer.

PWRITE APB bridge Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW.

PWDATA APB bridge Write data. This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide.

PREADY Slave interface Ready. The slave uses this signal to extend an APB transfer.

PRDATA Slave interface Read Data. The selected slave drives this bus during read cycles when PWRITE is LOW. This bus can be up to 32-bits wide.

PSLVERR Slave interface This signal indicates a transfer failure. APB peripherals are not required to support the PSLVERR pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this pin then the appropriate input to the APB bridge is tied LOW.