APB Protocol
工作项目中,不论用到的VIP是APB/AHB/AXI?工作的第一步,首先要做的工作是确认接口上的时钟和复位是否正常;VIP interface上的时钟和复位是否都正常,然后进行下一步的工作。可以帮助验证人员节省80%的debug时间!
目录
AMBA 3 APB Protocol Specification
1. 概述简介
可连接多种外围设备:I2C、SPI、UART
2. Signal Descriptions
PCLK Clock source Clock. The rising edge of PCLK times all transfers on the APB.
PRESETn System bus equivalent Reset. The APB reset signal is active LOW. This signal is normally connected directly to the system bus reset signal.
PADDR APB bridge Address. This is the APB address bus. It can be up to 32 bits wide and is driven by the peripheral bus bridge unit.
PSELx APB bridge Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. There is a PSELx signal for each slave.
PENABLE APB bridge Enable. This signal indicates the second and subsequent cycles of an APB transfer.
PWRITE APB bridge Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW.
PWDATA APB bridge Write data. This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is HIGH. This bus can be up to 32 bits wide.
PREADY Slave interface Ready. The slave uses this signal to extend an APB transfer.
PRDATA Slave interface Read Data. The selected slave drives this bus during read cycles when PWRITE is LOW. This bus can be up to 32-bits wide.
PSLVERR Slave interface This signal indicates a transfer failure. APB peripherals are not required to support the PSLVERR pin. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this pin then the appropriate input to the APB bridge is tied LOW.
3. Operating States
4 Transfers
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