Verilog练习：HDLBits笔记4

二、Verilog Language

Modules：Hierarchy

1、Modules

Problem Statement：

The figure below shows a very simple circuit with a sub-module.In this exercise, create one instanceof module mod_a then connect the module's three pins (in1，in2，and out) to your top-level module's three ports (wires a，b and out). The module mod_a is provided for you — you must instantiate it.

module top_module ( input a, input b, output out );
    
    // mod_a instance1 (a , b , out);                    By position
    // mod_a instance1 (.in1(a) , .in2(b) , .out(out));  By name

endmodule

 2、Connecting ports by position

Problem Statement：

 You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your top-level module's ports out1, out2, a, b, c, and d, in that order.

You are given the following module:

module mod_a ( output, output, input, input, input, input );

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
     mod_a instance1 (out1 , out2 , a , b , c , d);

endmodule

 3、Connecting ports by name 

Problem Statement：

You are given a module named mod_a that has 2 outputs and 4 inputs, in some order. You must connect the 6 ports by name to your top-level module's ports:

Port in mod_a	Port in top_module
output out1	out1
output out2	out2
input in1	a
input in2	b
input in3	c
input in4	d

You are given the following module:

module mod_a ( output out1, output out2, input in1, input in2, input in3, input in4);

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a instance1(.in1(a) , .in2(b) , .in3(c) , .in4(d) , .out1(out1) , .out2(out2));

endmodule

4、Three modules

Problem Statement：

You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

module top_module ( input clk, input d, output q );
    wire q1;
    wire q2;
    
    my_dff instance1(.clk(clk) , .d(d)  , .q(q1));
    my_dff instance2(.clk(clk) , .d(q1) , .q(q2));
    my_dff instance3(.clk(clk) , .d(q2) , .q(q));

endmodule

5、Modules and vectors

Problem Statement：

You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

module top_module ( 
    input        clk, 
    input  [7:0] d, 
    input  [1:0] sel, 
    
    output [7:0] q 
);
    wire   [7:0] q1; 
    wire   [7:0] q2; 
    wire   [7:0] q3;
    
    my_dff8 instance1(.clk(clk) , .d(d)  , .q(q1));
    my_dff8 instance2(.clk(clk) , .d(q1) , .q(q2));
    my_dff8 instance3(.clk(clk) , .d(q2) , .q(q3));
    
always@ (*)begin
	case (sel)
		4'd0 : 	 q = d;
		4'd1 : 	 q = q1;
		4'd2 : 	 q = q2;
		4'd3 : 	 q = q3;
    endcase
end
  
endmodule

 6、Adder 1

Problem Statement：

You are given a module add16 that performs a 16-bit addition. Instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result, after receiving the carry-out from the first adder. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored), but the internal modules need to in order to function correctly. (In other words, the add16 module performs 16-bit a + b + cin, while your module performs 32-bit a + b).

Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

module top_module(
    input  [31:0] a,
    input  [31:0] b,
    output [31:0] sum
);
    wire   [15:0] out1;
    wire   [15:0] out2;
    
    wire cout_cin;
    
    add16 instance1(.a(a[15:0]) ,  .b(b[15:0]) ,  .cin(1'd0) ,     .cout(cout_cin) , .sum(out1));
    add16 instance2(.a(a[31:16]) , .b(b[31:16]) , .cin(cout_cin) , .sum(out2));
    
    assign sum = {out2 , out1};

endmodule

  7、Adder 2

Problem Statement：

you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).

Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire   [15:0] out1;
    wire   [15:0] out2;
    
    wire cout_cin;
    
    add16 instance1(.a(a[15:0]) ,  .b(b[15:0]) ,  .cin(1'd0) ,     .cout(cout_cin) , .sum(out1));
    add16 instance2(.a(a[31:16]) , .b(b[31:16]) , .cin(cout_cin) , .sum(out2));
    
    assign sum = {out2 , out1};
    
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
    assign sum = a ^ b ^ cin;
    assign cout = (a&b) | (a&cin) | (b&cin);

endmodule

 8、Carry-select adder

Problem Statement：

In this exercise, you are provided with the same module add16 as the previous exercise, which adds two 16-bit numbers with carry-in and produces a carry-out and 16-bit sum. You must instantiate three of these to build the carry-select adder, using your own 16-bit 2-to-1 multiplexer.

Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

module top_module(
    input  [31:0] a,
    input  [31:0] b,
    output [31:0] sum
);
    wire [15:0] out1;
    wire [15:0] out2;
    wire [15:0] out3;
    wire [15:0] out4;
    
    wire sel;
    
    add16 instance1(.a(a[15:0])  , .b(b[15:0])  , .cin(1'b0) , .sum(out1) , .cout(sel));
    add16 instance2(.a(a[31:16]) , .b(b[31:16]) , .cin(1'b0) , .sum(out2));
    add16 instance3(.a(a[31:16]) , .b(b[31:16]) , .cin(1'b1) , .sum(out3));
    
    always@(*) begin
        case(sel)
            1'b0 : out4 = out2;
            1'b1 : out4 = out3;
        endcase
    end
    
    assign sum = {out4 , out1};
    

endmodule

 9、Adder-subtractor

Problem Statement：

You are provided with a 16-bit adder module, which you need to instantiate twice:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Use a 32-bit wide XOR gate to invert the b input whenever sub is 1. (This can also be viewed as b[31:0] XORed with sub replicated 32 times. Also connect the sub input to the carry-in of the adder.

module top_module(
    input  [31:0] a,
    input  [31:0] b,
    input  sub,
    
    output [31:0] sum
);
    wire   [15:0] out1;
    wire   [15:0] out2;
    wire   [31:0] b_sub;
    
    wire 		  cout_cin;
    
    assign b_sub = b ^ {32{sub}};
    
    add16 instance1(.a(a[15:0]) , .b(b_sub[15:0]) , .cin(sub) , .sum(out1) , .cout(cout_cin));
    add16 instance2(.a(a[31:16]) , .b(b_sub[31:16]) , .cin(cout_cin) , .sum(out2));
    
    assign sum = {out2 , out1};

endmodule