Verilog练习：HDLBits笔记6

二、Verilog Language

More Verilog Features

1、Conditional ternary operator

Problem Statement：

Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You'll probably want some wire vectors for the intermediate results.

module top_module (
    input  [7:0] a, b, c, d,
    output [7:0] min
);
    
    wire   [7:0]min1;
    wire   [7:0]min2;
    
    assign min1 = (a > b) ? b : a;
    assign min2 = (c > d) ? d : c;
    
    assign min = (min1 > min2) ? min2 : min1;

endmodule

2、Reduction operators

Problem Statement：

Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

module top_module (
    input [7:0] in,
    output parity
);
    assign parity = ^in[7:0];

endmodule

3、Reduction:Even wider gates

Problem Statement：

Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

• out_and: output of a 100-input AND gate.
• out_or: output of a 100-input OR gate.
• out_xor: output of a 100-input XOR gate.

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    assign out_and = &in[99:0];
    assign out_or  = |in[99:0];
    assign out_xor = ^in[99:0];

endmodule

 4、Combinational for-loop: Vector reversal2

Problem Statement：

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module( 
    input  [99:0] in,
    output [99:0] out
);
    integer i;
    
    always@(*)begin  
    	for(i = 0 ; i <= 99 ; i = i + 1)begin
            out[i] = in[99 - i];
    	end
    end
            
endmodule

5、Combinational for-loop:255-bit population count

Problem Statement：

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector. 

module top_module( 
    input  [254:0] in,
    output [7:0]   out 
);
    integer i;
    
    always@(*)begin
        out = 8'd0;
        for(i = 0 ; i <= 254 ; i = i + 1)begin
            out = out + in[i];
        end
    end
    
endmodule

 6、Generate for-loop:100-bit binary adder 2

Problem Statement：

Create a 100-bit binary ripple-carry adder by instantiating 100 full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[99] is the final carry-out from the last full adder, and is the carry-out you usually see.

module top_module( 
    input  [99:0] a, b,
    input  cin,
    output [99:0] cout,
    output [99:0] sum 
);
    
    generate  
        genvar i;
        for(i = 0;i <= 99;i = i + 1)begin:full_adder
            if(i == 0)begin
                assign cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin);
                assign sum [0] = a[0] ^ b[0] ^ cin; 
            end
            else begin
                assign cout[i] = (a[i] & b[i]) | (a[i] & cout[i-1]) | (b[i] & cout[i-1]);
                assign sum [i] = a[i] ^ b[i] ^ cout[i-1];       
            end
        end
    endgenerate

endmodule

 7、Generate for-loop:100-digit BCD adder

Problem Statement：

You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {
    input [3:0] a,
    input [3:0] b,
    input     cin,
    output   cout,
    output [3:0] sum );

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum 
);
    wire [399:0]cout_n;
    
    generate
        genvar i;
        for (i = 0;i <= 99;i = i + 1)begin:bcd_fadd
            if(i == 0)begin
                bcd_fadd u_bcd_fadd(
                    .a(a[3:0]),
                    .b(b[3:0]),
                    .cin(cin),
                    .cout(cout_n[i]),
                    .sum(sum[3:0])
                );
            end
            else begin
                bcd_fadd u_bcd_fadd(
                    .a(a[4*i+3:4*i]),
                    .b(b[4*i+3:4*i]),
                    .cin(cout_n[i-1]),
                    .cout(cout_n[i]),
                    .sum(sum[4*i+3:4*i])
                );
            end
        end 
        assign cout = cout_n[99];
    endgenerate 

endmodule