Verilog练习：HDLBits笔记18

五、Reading Simulations

Build a circuit from a simulation

1、Combinational circuit 1

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    input b,
    output q );

    assign q = a & b; 

endmodule

2、Combinational circuit 2

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = (c & d | ~c & ~d) & (a & b | ~a & ~b) | (~a & b | a & ~b) & (~c & d | c & ~d);

endmodule

3、Combinational circuit 3

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = (~a & b | a & ~b | a & b) & (~c & d | c & ~d | c & d); 

endmodule

4、Combinational circuit 4

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );

    assign q = c | b & ~c;

endmodule

5、Combinational circuit 5

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

Simulation 1

Simulation 2

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q 
);
    always@(*)begin
        case(c)
        	4'h0 : q <= b;
            4'h1 : q <= e;
            4'h2 : q <= a;
            4'h3 : q <= d;
            default : q <= 4'hf;
        endcase
    end

endmodule

6、Combinational circuit 6

Problem Statement：

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input [2:0] a,
    output [15:0] q 
); 
    always@(*)begin
        case(a)
        	3'd0 : q <= 16'h1232;
            3'd1 : q <= 16'haee0;
            3'd2 : q <= 16'h27d4;
            3'd3 : q <= 16'h5a0e;
            3'd4 : q <= 16'h2066;
            3'd5 : q <= 16'h64ce;
            3'd6 : q <= 16'hc526;
            3'd7 : q <= 16'h2f19;
        endcase
    end

endmodule

7、Sequence circuit 7

Problem Statement：

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input clk,
    input a,
    output q );
    
    always@(posedge clk)begin
    	q <= ~a;
    end

endmodule

8、Sequence circuit 8

Problem Statement：

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input clock,
    input a,
    output p,
    output q );
    
    always@(*)begin
        if(clock)
    		p <= a;
        else
            p <= p;
    end
    
    always@(negedge clock)begin
    	q <= p;
    end
    
endmodule

9、Sequence circuit 9

Problem Statement：

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input clk,
    input a,
    output [3:0] q 
);
    always@(posedge clk)begin
        if(a)
            q <= 4'd4;
        else if(q == 4'd6)
            q <= 4'd0;
        else
            q <= q + 1'd1;
    end

endmodule

10、Sequence circuit 10

Problem Statement：

This is a sequential circuit. The circuit consists of combinational logic and one bit of memory (i.e., one flip-flop). The output of the flip-flop has been made observable through the output state.

Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    always@(posedge clk)begin
        if(a == b)
            state <= a;
        else
            state <= state;
    end

    assign q = a ^ b ^ state;
    
endmodule