HDLbits ece241 2014 q3

最新推荐文章于 2024-09-13 13:02:08 发布

Zephyr_R

最新推荐文章于 2024-09-13 13:02:08 发布

阅读量66

点赞数

分类专栏： Verilog 文章标签： fpga开发 Powered by 金山文档

本文链接：https://blog.csdn.net/Zephyr_R/article/details/128582769

版权

Verilog 专栏收录该内容

15 篇文章 0 订阅

订阅专栏

文章描述了一个电路设计问题，要求仅使用一个4-to-1和多个2-to-1多路复用器来实现Karnaugh地图表示的逻辑功能，不允许使用其他逻辑门。提供了两种不同的Verilog模块实现方式，一种是传统的case语句，另一种是使用条件运算符直接连接多路复用器。

摘要由CSDN通过智能技术生成

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.

(The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.)

4-to-1

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    always @(*)
        begin
            case({c,d})
                2'd0:mux_in=4'b0100;
                2'd1:mux_in=4'b0001;
                2'd3:mux_in=4'b1001;
                2'd2:mux_in=4'b0101;
            endcase
        end
endmodule

3个四位 2-1

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    wire [3:0]sel0;
    wire [3:0]sel1;
    
    always @(*)
        begin
            case(c)
                1'd0:sel0=4'b0100;
                1'd1:sel0=4'b0101;
            endcase
        end
    always @(*)
        begin
            case(c)
                1'd0:sel1=4'b0001;
                1'd1:sel1=4'b1001;
            endcase
        end
    always @(*)
        begin
            case(d)
                1'd0:mux_in=sel0;
                1'd1:mux_in=sel1;
            endcase      
        end
endmodule

solution

module top_module (
    input c,
    input d,
    output [3:0] mux_in
);
    
    // After splitting the truth table into four columns,
    // the rest of this question involves implementing logic functions
    // using only multiplexers (no other gates).
    // I will use the conditional operator for each 2-to-1 mux: (s ? a : b)
    assign mux_in[0] = c ? 1 : d;          // 1 mux:   c|d
    assign mux_in[1] = 0;                  // No muxes:  0
    assign mux_in[2] = d ? 0 : 1;          // 1 mux:    ~d
    assign mux_in[3] = c ? d : 0;          // 1 mux:   c&d
    
endmodule