学习笔记 Exams/review2015 fsm

最新推荐文章于 2024-09-14 21:53:48 发布

Zephyr_R

最新推荐文章于 2024-09-14 21:53:48 发布

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本文描述了一个使用有限状态机控制的计时器设计，当接收到1101模式时启动，通过位移确定延迟时间，等待计数器计完后通知用户并等待确认。该FSM仅负责状态转移逻辑，不包含数据路径部分。

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We want to create a timer that:

is started when a particular pattern (1101) is detected,
shifts in 4 more bits to determine the duration to delay,
waits for the counters to finish counting, and
notifies the user and waits for the user to acknowledge the timer.

In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.

The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.

After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.

At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The state machine should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );

    parameter s0=0,s_1=1,s_11=2,s_110=3,sf_1=4,sf_2=5,sf_3=6,sf_4=7,s_count=8,s_done=9;
    reg[3:0] state,next_state;

    always @(posedge clk)
    begin if (reset) state <= s0;
          else state <= next_state;
    end

    always @(*)
    begin
        case(state)
        s0:    next_state = (data ? s_1:s0);  
        s_1:   next_state = (data ? s_11:s0);   //s1:1xxx
        s_11:  next_state = (data ? s_11:s_110);   //s2:11xx
        s_110: next_state = (data ? sf_1:s0);   //s3:110x
        sf_1:  next_state = sf_2;               //1101 & shift_ena=1
        sf_2:  next_state = sf_3;
        sf_3:  next_state = sf_4;
        sf_4:  next_state = s_count;
        s_count: next_state = (done_counting ? s_done : s_count);
        s_done: next_state = (ack ? s0:s_done);

        endcase
    end 

    assign shift_ena = (state==sf_1)|(state==sf_2)|(state==sf_3)|(state==sf_4);
    assign counting = (state==s_count);
    assign done = (state==s_done);

endmodule