2020年05月_德华的神兜兜

原创 hdlbits_Fsm_hdlc

https://hdlbits.01xz.net/wiki/Fsm_hdlc有errormodule top_module( input clk, input reset, // Synchronous reset input in, output disc, output flag, output err); reg [7:0]d; always @(posedge clk) begin

2020-05-31 19:41:29 403 2

https://hdlbits.01xz.net/wiki/Fsm_serialdata看图发现先进的是bit0module top_module( input clk, input in, input reset, // Synchronous reset output [7:0] out_byte, output done); // reg [9:0] d; // Use FSM from Fsm_serial paramete

2020-05-29 20:56:57 470

原创 hdlbits_Exams/review2015_shiftcount

https://hdlbits.01xz.net/wiki/Exams/review2015_shiftcountmodule top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always @(posedge clk) begin if (shift_ena) q&

2020-05-27 19:23:58 294

原创 hdlbits_Exams/review2015_fsmseq

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmseq用LFSR 写更简单一些module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); reg [3:0] d; always @(posedge clk) begin

2020-05-27 19:19:04 424 1

原创 RAM_verilog_code

/* * Random Access Memory (RAM) with * 1 read port and 1 write port */module ram (clk_write, address_write, data_write, write_enable, clk_read, address_read, data_read); parameter D_WIDTH = 16; parameter A_WIDTH = 4; parameter A_MAX = 16;

2020-05-26 17:22:29 369

原创 Exams/review2015 count1k_hdbits

https://hdlbits.01xz.net/wiki/Exams/review2015_count1kBuild a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.module top_module ( input clk, input reset

2020-05-25 19:45:24 830

原创 hdlbits_Fsm_serial

module top_module( input clk, input in, input reset, // Synchronous reset output done); parameter stop = 0,b0=1,b1=2,b2=3,b3=4,b4=5,b5=6,b6=7,b7=8,stop_ok=9,stop_notok=10,start = 11; //parameter idle = 0,start = 1,b0=2,b1=3,b2,=4,

2020-05-25 16:46:32 428

原创 hdlbits_Fsm_ps2data

mark: 还有errormodule top_module( input clk, input [7:0] in, input reset, // Synchronous reset output [23:0] out_bytes, output done); // reg [7:0]b0,b1,b2,b3; // FSM from fsm_ps2 reg [1:0]state,next; parameter S0=0,S

2020-05-21 13:44:37 461

原创 hdlbits_Fsm_onehot

module top_module( input in, input [9:0] state, output [9:0] next_state, output out1, output out2); parameter S0 = 10'h1,S1 =10'h2,S2=10'h4,S3=10'h8,S4=10'h10,S5=10'h20,S6=10'h40,S7=10'h80,S8=10'h100,S9=10'h200; always...

2020-05-20 15:37:15 366 1

原创 hdlbits_Lemmings3

有errormodule top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, input dig, output walk_left, output walk_right, output aaah, output di

2020-05-20 12:19:09 172

原创 hdlbits_tff

module top_module (); reg clk; reg reset,t; reg q; always #10 clk=~clk; always #20 t=~t; initial begin clk = 0; reset = 0; t=0; #30 reset=1; #10 reset=0;

2020-05-19 16:44:17 138

原创 hdlbits_tb2

module top_module(); reg clk,in,out; reg [2:0] s; always #5 clk = ~clk; initial begin clk = 0; in = 0; s = 3'h2; #10 s=3'h6; #10 s=3'h2;in=1; #10 in = 0;s=3'h7;

2020-05-19 15:38:15 168

原创 hdlbits_Fsm_ps2

module top_module( input clk, input [7:0] in, input reset, // Synchronous reset output done); // parameter S0 =0,S1=1,S2=2,S3=3; reg [1:0] state , next; // State transition logic (combinational) always @(*) begi

2020-05-19 14:10:51 532 1

原创 hdlbits_Lemmings2

module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, input ground, output walk_left, output walk_right, output aaah ); parameter WL=0,WR=1,AH_L=2

2020-05-19 11:59:58 293

原创 Lemmings1_hdlbits

module top_module( input clk, input areset, // Freshly brainwashed Lemmings walk left. input bump_left, input bump_right, output walk_left, output walk_right); // // parameter LEFT=0, RIGHT=1, ... reg state, next_state

2020-05-19 11:41:44 187

原创 Fsm3s_hdlbits

module top_module( input clk, input in, input reset, output out); // parameter A=0,B=1,C=2,D=3; reg [1:0]state,next; // State transition logic always @(*) begin case (state) A: next

2020-05-18 22:15:56 270

原创 Fsm3_hdlbits

module top_module( input clk, input in, input areset, output out); // parameter A=0,B=1,C=2,D=3; reg [1:0]state,next; // State transition logic always @(*) begin case (state) A: nex

2020-05-18 22:11:55 278

原创 Fsm3onehot_hdlbits

module top_module( input in, input [3:0] state, output [3:0] next_state, output out); // parameter A=0, B=1, C=2, D=3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] = state[A]&amp

2020-05-18 21:56:01 787

原创 Fsm3comb_hdlbits

module top_module( input in, input [1:0] state, output [1:0] next_state, output out); // parameter A=0, B=1, C=2, D=3; //reg state, next; // State transition logic: next_state = f(state, in) always @ (*) begin

2020-05-18 16:37:19 662

原创 Fsm2s_hdlbits

module top_module( input clk, input reset, // Synchronous reset to OFF input j, input k, output out); // parameter OFF=0, ON=1; reg state, next_state; always @(*) begin // State transition logic case

2020-05-18 14:41:23 183

原创 Fsm2_hdlbits

module top_module( input clk, input areset, // Asynchronous reset to OFF input j, input k, output out); // parameter OFF=0, ON=1; reg state, next_state; always @(*) begin // State transition logic cas

2020-05-18 14:09:41 212

原创 Fsm1_hdlbits

状态机学习link：https://wenku.baidu.com/view/9e44f7650066f5335a8121e3.htmlmodule top_module( input clk, input areset, // Asynchronous reset to state B input in, output out);// parameter A=0, B=1; reg state, next_state; alway

2020-05-17 23:34:38 601

原创 Rule110_hdlbits

没有化简module top_module( input clk, input load, input [511:0] data, output [511:0] q); reg [511:0 ]q_l, q_r; assign q_l = {1'b0, q[511:1]}; assign q_r = {q[510:0] , 1'b0}; always @ (posedge clk) begin if

2020-05-15 18:32:34 794 1

原创 Rule90_hdlbits

module top_module( input clk, input load, input [511:0] data, output [511:0] q ); always @ (posedge clk) begin if (load) q <= data; else begin

2020-05-15 16:47:05 1497

原创 Exams/2014 q4b_hdlbits

module top_module ( input [3:0] SW, input [3:0] KEY, output [3:0] LEDR); // reg q1,q2,q3,q4; MUXDFF n4( .clk(KEY[0]), .ain(KEY[3]), .bin(LEDR[3]), .cin(SW[3]), .sel1(KEY[1]), .sel2(KEY[2]

2020-05-15 15:21:26 647

原创 Exams/m2014 q4k_hdlbits

module top_module ( input clk, input resetn, // synchronous reset input in, output out); reg [3:1] q; always @ (posedge clk) begin if (~resetn) {q,out} <= 4'b0; else

2020-05-15 11:28:24 1014 1

原创 Lfsr32_hdlbits

module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q); reg [31:0] q_next; always @ (*) begin q_next = {q[0], q[31:1]}; q_next[31] = q[0] ^ 1'b0;

2020-05-15 11:14:47 1037

原创 Mt2015 lfsr_hdlbits

module mux2to1( input ain, input bin, input sel, output cout); assign cout = sel?bin:ain; // sel = 0, cout = cin ; sel =1 ,cout = bin; endmodulemodule top_module ( input [2:0] SW, // R input [1:0] KEY, // L and clk outp

2020-05-15 11:00:24 394

原创 Lfsr5_hdlbits

module top_module( input clk, input reset, // Active-high synchronous reset to 5'h1 output [4:0] q); always @(posedge clk) begin if (reset) q<=5'h1; else begin

2020-05-15 10:43:00 532

原创 hdlbits_shift18

module top_module( input clk, input load, input ena, input [1:0] amount, input [63:0] data, output reg [63:0] q); always @ ( posedge clk) begin if (load) q <= data; else

2020-05-14 19:41:15 469

原创 Rotate100_hdlbits

module top_module( input clk, input load, input [1:0] ena, input [99:0] data, output reg [99:0] q); always @ (posedge clk) begin if (load) q <= data; else if (ena == 2'b10)

2020-05-14 18:58:33 438

原创 Shift4_hdlbits

module top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output reg [3:0] q); always @ (posedge clk or posedge areset) begin if (areset)

2020-05-14 15:52:37 736

原创 Countbcd_hdlbits

module bcdcount(input clk, input reset, input ena, //output reg cout, output reg [3:0] q); //reg cout; //reg [3:0] q; always @(posedge clk) begin if (reset == 1

2020-05-14 11:08:33 1296

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