module top_module ();
reg clk;
reg reset,t;
reg q;
always #10 clk=~clk;
always #20 t=~t;
initial
begin
clk = 0;
reset = 0;
t=0;
#30 reset=1;
#10 reset=0;
end
tff inst1(
.clk(clk),
.reset(reset),
.t(t),
.q(q)
);
endmodule
hdlbits_tff
最新推荐文章于 2024-05-02 17:04:51 发布