module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @ ( posedge clk)
begin
if (load)
q <= data;
else if (ena)
begin
if (amount == 2'b00)
q <= q <<1;
else if (amount == 2'b01)
q <= q <<8;
else if (amount == 2'b10)
q <= (q/2) | 64'b0 | (q & 64'h8000000000000000);
else if (amount == 2'b11)
q <= {{8{q[63]}}, q[63-:56]};
end
end
endmodule
hdlbits_shift18
最新推荐文章于 2024-01-31 20:31:30 发布