UVM overwrite

    `ifndef TEST_COLLECTION__SV
    `define TEST_COLLECTION__SV

    `include "router_env.sv"

    class test_base extends uvm_test;
      `uvm_component_utils(test_base)
  router_env env;

  function new(string name, uvm_component parent);
    super.new(name, parent);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);
    env = router_env::type_id::create("env", this);
  endfunction

//
// The start_of_simulation_phase method from lab1 is moved to final_phase
// for the convinience of seeing the topology and factory registry at the
// end of simulation.  In practice, you should implement both phases to
// display the topology and the factory registry.
//
  virtual function void final_phase(uvm_phase phase);
    super.final_phase(phase);
    `uvm_in