Verilog刷题记录2

module top_module ( input clk, input d, output q );
    wire q1,q2;
    my_dff instance1(.clk,.d(d),.q(q1));
    my_dff instance2(.clk,.d(q1),.q(q2));
    my_dff instance3(.clk,.d(q2),.q(q));
endmodule

 

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cin,cout;
    reg [15:0]sum1,sum2;
    add16 ins1(.a(a[15:0]),.b(b[15:0]),.cin(1'b0),.sum(sum[15:0]),.cout(cout));
    add16 ins2(.a(a[31:16]),.b(b[31:16]),.cin(1'b0),.sum(sum1));
    add16 ins3(.a(a[31:16]),.b(b[31:16]),.cin(1'b1),.sum(sum2));
    always @(*)begin
        case(cout)
        1'b1:sum[31:16]=sum2;   
        1'b0:sum[31:16]=sum1;
        endcase
    end
endmodule

 

module top_module (
	input [254:0] in,
	output reg [7:0] out
);

	always @(*) begin	// Combinational always block
		out = 0;
		for (int i=0;i<255;i++)
			out = out + in[i];
	end
	
endmodule

 

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
	assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin;
     assign sum[0]  = a[0] ^ b[0] ^ cin;
     integer i;
    always @ (*) begin
        for (i=1; i<100; i++) begin
             cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1];
             sum[i]  = a[i] ^ b[i] ^ cout[i-1];
        end
       
    end
endmodule