HDLBits练习记录——12 Hour clock

chelly4664

于 2023-07-28 17:38:28 发布

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HDLBits练习记录——12 Hour clock
题目：Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

在这里插入图片描述

module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);

reg [3:0] h_ones,h_tens,m_ones,m_tens,s_ones,s_tens;
always @(posedge clk) begin
    if(reset)begin
        s_ones <= 4'd0; 
        m_ones <= 4'd0;
        h_ones <= 4'd2;
        s_tens <= 4'd0; 
        m_tens <= 4'd0;
        h_tens <= 4'd1;
        pm <= 1'd0;
        temp_pm <= 1'd0;
    end
    else if(ena)begin    
        if(s_ones == 8'd9&&s_tens == 8'd5)begin
        	s_ones <=8'b0;
            s_tens <=8'b0;
 	   	end
    	else begin
        	s_ones <= s_ones + 4'b1;
            if(s_ones ==9)begin
                s_tens <= s_tens + 4'b1;
                s_ones <= 1'b0;
            end
    	end
    
        if(m_ones == 8'd9&&m_tens == 8'd5&&s_ones == 8'd9&&s_tens == 8'd5)begin
        	m_ones <=8'd0;
            m_tens <=8'd0;
    	end
    	else if(s_ones == 8'd9&&s_tens == 8'd5)begin
        	m_ones <= m_ones + 4'b1;
            if(m_ones ==9)begin
                m_tens <= m_tens + 4'b1;
                m_ones <= 1'b0;
            end
    	end

        if(h_ones == 8'd2&&h_tens == 8'd1&& m_ones == 8'd9&&m_tens == 8'd5&&s_ones == 8'd9&&s_tens == 8'd5)begin
        	h_ones <=8'd1;
            h_tens <=8'd0;
    	end
        else if(m_ones == 8'd9&&m_tens == 8'd5&&s_ones == 8'd9&&s_tens == 8'd5) begin
        	h_ones <= h_ones + 4'd1;
            if(h_ones ==9)begin
                h_tens <= h_tens + 4'd1;
                h_ones <= 1'b0;
            end
    	end
        
        if(h_ones == 8'd1&&h_tens == 8'd1&m_ones == 8'd9&&m_tens == 8'd5&&s_ones == 8'd9&&s_tens == 8'd5)    
            pm <= ~pm;
    end
end
    assign ss = {s_tens,s_ones};
    assign mm = {m_tens,m_ones};
    assign hh = {h_tens,h_ones};

endmodule