用Verilog实现12_hour_clock(HDLbits的Count clock题)

Title：Count clock
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
题目的意思就是创建一个十二小时的时钟，2位BCD码（8位宽）hh、mm、ss分别表示时分秒，pm则表示上午、下午（当pm=0便是上午，pm=1表示下午），然后同步复位reset=1’b1使能，将时钟重置为12：00：00，同时使能位ena=1’b1表示时钟的运行，而且reset优先级大于ena。
时序图如下：

Module Declaration
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);

废话不多说，直接上代码

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss
    ); 
    
    wire ss_en,mm_en,hh_en;
    assign ss_en = ena;
    assign mm_en = ss_en&(ss == 8'h59);
    assign hh_en = mm_en&(mm == 8'h59);
    
    mm_ss u0_mm_ss(clk,reset,ss_en,ss);    
    mm_ss u1_mm_ss(clk,reset,mm_en,mm);
    hh u_hh(clk,reset,hh_en,hh);
    
    always@(posedge clk)begin
        if(reset)
        	pm <= 1'b0;
        else begin
            if((hh == 8'h11)&(mm == 8'h59)&(ss == 8'h59)) //当12：00：00翻转pm
            	pm <= ~pm;
            else
                pm <= pm;
        end
    end  
endmodule

//时模块
module hh(
	input            clk  ,
    input            reset,
    input            en   ,
    output  [7:0]    hh
);
    wire [3:0] counter1,counter0;
    assign hh = {counter1,counter0};
    h0_bcdcounter u_h0_bcdcounter(clk,reset,en,counter1,counter0);
    h1_bcdcounter u_h1_bcdcounter(clk,reset,(en&((hh==8'h12)|(counter0==4'h9))),counter1);//当九点或十二点使能来时，翻转时十位；
    
endmodule  

//分秒模块
module mm_ss(
	input            clk  ,
    input            reset,
    input            en   ,
    output  [7:0]    mm_ss
);
    wire [3:0] counter1,counter0;
    assign mm_ss = {counter1,counter0};
    bcdcounter u0_bcdcounter(clk,reset,en,4'h0,4'h9,counter0);
    bcdcounter u1_bcdcounter(clk,reset,(en&(counter0==4'h9)),4'h0,4'h5,counter1);
endmodule 

//bcd码计数
module bcdcounter(
	input            clk     ,
    input            reset   ,
    input            en      ,
    input      [3:0] resetnum, //这里设置本来想时也可以例化这个，结果发现不可以
    input      [3:0] loadtnum,
    output reg [3:0] counter
);
    always@(posedge clk)begin
        if(reset)
            counter <=resetnum;
        else begin
            if(en)begin
                if(counter == loadtnum)
                	counter <= 4'h0;
                else
                	counter <= counter + 1'b1;
            end
            else
            	counter <= counter;
        end
    end
endmodule    

//时个位
module h0_bcdcounter( 
	input            clk     ,
    input            reset   ,
    input            en      ,
    input      [3:0] h1      ,    
    output reg [3:0] counter
);
    always@(posedge clk)begin
        if(reset)
            counter <=4'h2;
        else begin
            if(en)begin
                if(counter == 4'h9)
                	counter <= 4'h0;
                else if((h1==4'h1)&(counter == 4'h2)) //当12点使能来时，将时个位置1
                    counter <= 4'h1;
                else
                	counter <= counter + 1'b1;
            end
            else
            	counter <= counter;
        end
    end
endmodule 

//时十位
module h1_bcdcounter(  
	input            clk     ,
    input            reset   ,
    input            en      ,
    output reg [3:0] counter
);
    always@(posedge clk)begin
        if(reset)
            counter <=4'h1;
        else begin
            if(en)begin
                if(counter == 4'h1)
                	counter <= 4'h0;
                else
                	counter <= counter + 1'b1;
            end
            else
            	counter <= counter;
        end
    end
endmodule 

仿真图如下：