vivado 常见引脚约束文件的写法--通配符及bit文件压缩

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已于 2022-09-01 17:18:10 修改

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分类专栏： zynq 文章标签： fpga开发

于 2022-09-01 17:17:39 首次发布

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#Clock cycle period constraint
create_clock -period 10.000 -name sysclk [get_ports diff_clock_clk_p]

set_property PACKAGE_PIN AH22 [get_ports diff_clock_clk_p]
set_property IOSTANDARD DIFF_SSTL12 [get_ports diff_clock_clk_p

set_property IOSTANDARD LVCMOS18 [get_ports {LED_o[*]}]
set_property PACKAGE_PIN A21 [get_ports {LED_o[1]}]
set_property PACKAGE_PIN A18 [get_ports {LED_o[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports RSTn_i]
set_property PACKAGE_PIN K24 [get_ports RSTn_i]

#bit compress
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]