verilog刷题笔记006

xiaobaibaizzf

已于 2022-04-05 17:28:04 修改

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文章标签： fpga开发

于 2022-04-04 22:46:30 首次发布

本文链接：https://blog.csdn.net/cxiaobaizzf/article/details/123962343

版权

该博客介绍了如何使用Verilog语言设计一个有限状态机(FSM)来实现串行数据的奇偶校验功能。代码中包含了状态机的状态转换逻辑和数据路径，并且在接收到数据时更新校验位。同时，还添加了对非法状态的处理和同步复位功能。

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Fsm serialdp的一种解法
预置代码：

module parity (
    input clk,
    input reset,
    input in,
    output reg odd);

    always @(posedge clk)
        if (reset) odd <= 0;
        else if (in) odd <= ~odd;

endmodule

我的Verilog描述

// Use FSM from Fsm_serial
	module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Modify FSM and datapath from Fsm_serialdata
    reg [3:0] state;
    reg [3:0] next_state;
    reg odd;
    wire p_reset = reset | (~(state>=1&&state<=8));//不是接收数据或者同步复位奇校验都应该置零
    parameter WAIT = 4'd0, CONFUSED = 4'd11, C_WAIT = 4'd12;
    always@(*)begin
        if(state == WAIT)begin
            if(in == 0) next_state =  1;
            else next_state = C_WAIT;
        end
        else if(state == C_WAIT)begin
            if(in == 0) next_state = 1;
            else next_state = C_WAIT;
        end
        else if(state >=1 && state <=8)begin
            next_state = state +1;
        end
        else if(state == 9)begin
            if(in == ~odd) next_state = state + 1;//因为状态8的时候仍然可以再使odd取反一次
            else next_state = CONFUSED;
        end
        else if(state == 10)begin
            if(in == 1) next_state = WAIT;
            else next_state = CONFUSED;
        end
        else if (state == CONFUSED)begin
            if(in == 1) next_state = C_WAIT;
            else next_state = CONFUSED;
        end
    end
    
    
    always@(posedge clk)begin
        if(reset) state <= C_WAIT;
        else state <= next_state;
        if(state >=1 && state <=8)
            out_byte[state-1] = in;
    end
    
    assign done = (state == WAIT);
    // New: Add parity checking.
    parity parity1(clk,p_reset,in,odd);

endmodule