Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.
创建带同步复位的8位的D触发器
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always@ (posedge clk)
if(reset)
q <= 8'd0;
else
q <= d;
endmodule