HDLBits 刷题之我的代码（全）—（Verification_Reading Simulations-Build a circuit from a simulation waveform）

#1

module top_module (
    input a,
    input b,
    output q );//

    assign q = a & b; // Fix me

endmodule

#2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = ((~a) & (~b) & (~c) & (~d)) | ((a) & (b) & (~c) & (~d)) | ((~a) & (b) & (~c) & (d)) | ((a) & (~b) & (~c) & (d)) | ((~a) & (~b) & (c) & (d)) | 
        ((a) & (b) & (c) & (d)) | ((~a) & (b) & (c) & (~d)) | ((a) & (~b) & (c) & (~d)); 

endmodule

#3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    //assign q = (a & d) | (a & c) | (b & d) | (b & c); // Fix me
    assign q = (a | b) & (d | c) ;

endmodule

#4

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b | c; // Fix me

endmodule

#5

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );
    always @(*) begin
        case(c)
            0: q = b;
            1: q = e;
            2: q = a;
            3: q = d;
            default: q = 'hf;
        endcase
    end
endmodule

#6

module top_module (
    input [2:0] a,
    output [15:0] q ); 
    always @(*) begin
        case(a) 
            0: q = 'h1232;
            1: q = 'haee0;
            2: q = 'h27d4;
            3: q = 'h5a0e;
            4: q = 'h2066;
            5: q = 'h64ce;
            6: q = 'hc526;
            7: q = 'h2f19;
            default: q = 'h1232;
        endcase
    end
endmodule

#7

module top_module (
    input clk,
    input a,
    output q );
    always @(posedge clk) begin
		q <= ~a;   
    end
endmodule

#8

module top_module (
    input clock,
    input a,
    output p,
    output q );
    always@(*) begin
        if(clock) p=a;
        else p=p;
    end
    always @(negedge clock) begin
      q<=p;
       
    end 
endmodule

#9

module top_module (
    input clk,
    input a,
    output [3:0] q );
    always @(posedge clk) begin
        if(a == 'd1) begin
            q <= 'd4;
        end
        else begin
            if(q == 'd6) 
                q <= 'd0;
            else
                q <= q + 'd1;
        end
    end
endmodule

#10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    reg nstate;
    always @(*) begin
        case(state)
            0: begin
                if(a && b)
                    nstate <= 1;
                else
                    nstate <= 0;
            end
            1: begin
                if((~a) && (~b))
                    nstate <= 0;
                else
                    nstate <= 1;
            end
            default: nstate <= 0;
        endcase
    end
    always @(posedge clk) begin
        state <= nstate;
    end
    
    assign q = state ? (a ^~ b):(a ^ b);

endmodule

#11