HDLBits 刷题之我的代码（全）—（Circuits-Combinational Logic_Basic Gates）

#1

module top_module (
    input in,
    output out);
	assign out = in;
endmodule

#2

module top_module (
    output out);
	assign out = 1'b0;
endmodule

#3

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~(in1 | in2);
endmodule

#4

module top_module (
    input in1,
    input in2,
    output out);
    assign out = in1 & (~in2);
endmodule

#5

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    assign out = (in1 ^~ in2) ^ in3;
endmodule

#6

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a & b;
    assign out_or = a | b;
    assign out_xor = a ^ b;
    assign out_nand = ~(a & b);
    assign out_nor = ~(a | b);
    assign out_xnor = a ^~ b;
    assign out_anotb = a &(~b);

endmodule

#7

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule

#8

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f = ((~x3) & x2) | (x3 & x1);

endmodule

#9

module top_module ( input [1:0] A, input [1:0] B, output reg z ); 
    always @(*)begin
    if(A == B)
        z = 'd1;
    else 
        z = 'd0;
    end
endmodule

#10

module top_module (input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule

#11

module top_module ( input x, input y, output z );
	assign z = x ^~ y;
endmodule

#12

module top_module (input x, input y, output z);
    wire z1,z2,z3,z4;
    wire w1,w2;
    assign z1 = (x ^ y) & x;
    assign z2 = x ^~ y;
    assign z3 = (x ^ y) & x;
    assign z4 = x ^~ y;
    assign w1 = z1 | z2;
    assign w2 = z3 & z4;
    assign z = w1 ^ w2;
endmodule

#13

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer = ring ? (vibrate_mode ? 'd0:'d1) : 'd0;
    assign motor = ring ? (vibrate_mode ? 'd1:'d0) : 'd0;
endmodule

#14

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    assign heater = mode ? (too_cold ? 1:0):0;
    assign aircon = mode ? 0:(too_hot ? 1:0);
    assign fan = (fan_on | heater | aircon) ? 1:0;
endmodule

#15

module top_module( 
    input [2:0] in,
    output [1:0] out );
    assign out = in[0] + in[1] + in[2];
endmodule

#16

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_both = in[2:0] & (in >> 1);
    assign out_any[3:1] = in[2:0] | in[3:1];
    assign out_different = {in[3] ^ in[0],in[3] ^ in[2],in[2] ^ in[1],in[1] ^ in[0]};
endmodule

#17

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    assign out_both = in[98:0] & (in >> 1);
    assign out_any[99:1] = in[98:0] | in[99:1];
    assign out_different = ({in[0],in[99:1]}) ^ in;
endmodule