module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
//state declaration
parameter wl=3'd0,wr=3'd1,fl=3'd2,fr=3'd3,dl=3'd4,dr=3'd5,f=3'd6;
reg [2:0] s;
reg [31:0] cnt;//计数器,由于不知道ground返回1之前持续多少周期,所以设置最大位宽。
wire flag;//ground返回1之间持续0的周期数超过20标志
//state transition
always@(posedge clk or posedge areset)begin
if(areset)begin
s<=wl;
end
else begin
case(s)
wl:if(!ground)//be care of the priorities of the inputs
s<=fl;
else if(ground&dig)
s<=dl;
else if(bump_left)
s<=wr;
wr:if(!ground)
s<=fr;
else if(ground&dig)
s<=dr;
else if(bump_right)
s<=wl;
fl:if(ground&&~flag)//相对于lemming3的变化仅为fl下ground为1时的两种去向
s<=wl;
else if(ground&&flag)//当满足题设条件时陷入f状态
s<=f;
fr:if(ground&&~flag)
s<=wr;
else if(ground&&flag)
s<=f;
dl:if(!ground)
s<=fl;
dr:if(!ground)
s<=fr;
default:s<=s;
endcase
end
end
always@(posedge clk or posedge areset)
if(areset)
cnt<=0;
else
cnt<=aaah?cnt+1:0;
//output assignments
assign flag=(cnt>=5'd20)?1'b1:1'b0;
assign walk_left=~aaah&&(s==wl)&&~digging;
assign walk_right=~aaah&&(s==wr)&&~digging;
assign aaah=(s==fl|s==fr);
assign digging=(s==dl|s==dr)&&(~aaah);
endmodule