HDLBits练习Fsm Ps2
由提示可知需要设置4个状态,复位后读取Byte,若该Byte的Byte[3]=1,则读取下一个Byte,否则需要等到新的Byte[3]=1的数据,才能开始状态跳转,然后等待两个周期后输出一周期的done高电平。因为done持续一个周期,此时已经读取了新的数据,若Byte[3]=1,则需跳到Byte2。
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter B1=2'd0,B2=2'd1,B3=2'd2,Dn=2'd3;
reg [1:0] state,next_state;
// State transition logic (combinational)
always@(*)begin
case(state)
B1:next_state=in[3]?B2:B1;
B2:next_state=B3;
B3:next_state=Dn;
Dn:next_state=in[3]?B2:B1;
endcase
end
// State flip-flops (sequential)
always@(posedge clk)begin
if(reset)
state<=B1;
else
state<=next_state;
end
// Output logic
//由于需要保持一个周期高电平,所以选择了时序逻辑输出done,
//且done在state==B3后就拉高,同时需要满足非复位。
always@(posedge clk)
if(state==B3&&~reset)
done<=1'd1;
else
done<=1'd0;
endmodule
但其实3个状态也是可以的。
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter B1=2'd0,B2=2'd1,B3=2'd2;
reg [1:0] state,next_state;
// State transition logic (combinational)
always@(*)begin
case(state)
B1:next_state=in[3]?B2:B1;
B2:next_state=B3;
B3:next_state=B1;//跳到Byte3之后直接跳到Byte1,经过Byte1判断后决定是否进行状态跳转
endcase
end
// State flip-flops (sequential)
always@(posedge clk)begin
if(reset)
state<=B1;
else
state<=next_state;
end
// Output logic
always@(posedge clk)
if(state==B3&&~reset)
done<=1'd1;
else
done<=1'd0;
endmodule