CTS相关知识点记录2

1、ICG

Integrated clock-gating (ICG) cell

clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal. clock gating functionally requires only an AND or OR  gate. Consider you were using an AND gate with clock. The high EN edge may come anytime and may not coincide with a clock edge. In that case the output of the AND gate will be a 1 for less time than the clock’s duty cycle. You in turn end up with a glitch in your clock signal. To avoid this, a special kind of clock gating cells are used, that synchronizes the EN with a clock edge. These are call integrated clock gating cells or ICG. [1]

ICG有两种形式：

(1)Using AND gate with high EN

(2)Using OR gate with high EN

2、mode by mode、merge mode、multi scenario mode

merge mode：将func mode和scan mode同时优化。

mode by mode：顺序优化

 

 

 

 

 

 

 

 

 

 

[1]https://vlsi.pro/integrated-clock-gating-cell/