Power Mode And State

https://semiengineering.com/power-mode-and-state/

Power Mode And State

By Luke Lang
Low-power designs that use power shutoff (PSO) and multiple-supply voltage (MSV) will have circuits that operate at various voltages, including no voltage. To describe the combination of allowable voltages in a design, CPF uses power mode, and UPF 1.0 uses power state.

In CPF, each power mode represents one combination of the states of all power domains. In UPF 1.0, each power state represents one combination of the voltages of all supply nets. It is much easier to explain this concept through an example.

Let’s assume we have the block below with 1.0 V always-on VDD (PDtop) driving into a power switch. The output of the power switch is VDD1 (PD1).