1.新建compile.tcl文件,假如FPGA顶层模块名为zynq_top_ps,其内容为:
synth_design -top zynq_top_ps
opt_design
place_design
route_design
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
write_debug_probes -force zynq_top_ps.ltx
write_bitstream -force -bin_file zynq_top_ps.bit
2.新建run脚本文件(shell脚本),其内容为:
vivado -mode tcl zynq_top_ps.xpr -source compile.tcl