选题二——智力抢答器的课程设计

一，实验内容，要求及目的

二，实验代码
1，module alldesign(reset,clock,din1,din2,din3,din4,clear,beep,number,cnt);
input reset,clock;
input din1,din2,din3,din4,clear;
output beep;
output [7:0] number,cnt;

wire clklk;
wire clklhz;
wire start;

clkdiv iunit1(reset,clock,clklhz);
qiangda iunit2(clock,din1,din2,din3,din4,clear,number,start);
daojishi iunit3(reset,clock/clklhz/,start,beep,cnt);
endmodule

2，module clkdiv(reset,clock,clklhz);
input reset,clock;
output clklhz;
reg clklhz;
reg[24:0] countl;
always@(posedge clock or posedge reset)
begin
if(reset)
countl<=0;
else if(countl==25’d25000000)
begin
clklhz<=~clklhz;
countl<=0;
end
else
countl<=countl+1;
end
endmodule

3，module qiangda(clock,din1,din2,din3,din4,clear,number,start);
input clock,clear;
input din1,din2,din3,din4;
output [7:0] number;
output start;
reg [7:0] number;
reg start;
reg block;

always@(posedge clock)
begin
if(!clear)
begin
block=0;