FPGA自学：Delay延迟

最新推荐文章于 2024-04-23 12:34:38 发布

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最新推荐文章于 2024-04-23 12:34:38 发布

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分类专栏：逻辑时序文章标签：延迟

本文链接：https://blog.csdn.net/leosynen/article/details/103758579

版权

本文介绍了在FPGA中如何实现信号延迟输出的方法，通过具体的代码示例和仿真结果，详细阐述了延迟几个时钟周期的技术要点。

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如何将某信号延迟输出几个时钟？

编写代码如下：

module Delay(clk,rst,datavalid,datadelay1,datadelay2,datadelay3);

input clk;
input rst;
input datavalid;
output datadelay1,datadelay2,datadelay3;

reg z1,z2,z3,z4,z5,z6,z7,z8;

always @(posedge clk or negedge rst)
if(!rst)
begin
	z1<=0;
	z2<=0;
	z3<=0;
	z4<=0;
	z5<=0;
	z6<=0;
	z7<=0;
	z8<=0;
end
else begin
	z1<=datavalid;
	z2<=z1;
	z3<=z2;
	z4<=z3;
	z5<=z4;
	z6<=z5;
	z7<=z6;
	z8<=z7;	
end

assign datadelay1 = z1;
assign datadelay2 = z4;
assign datadelay3 = z8;

endmodule

编写仿真文件：

`timescale 1ns/1ns

//定义模块
module Delay_tb;

//定义激励
reg clk_tb;
reg rst_tb;
reg datavalid_tb;
wire datadelay1_tb;
wire datadelay2_tb;
wire datadelay3_tb;

//例化连线
Delay Delay1(
	.clk(clk_tb),
	.rst(rst_tb),
	.datavalid(datavalid_tb),
	.