PCIE link

link是两个设备之间的二对双向差分线连接起来的。时钟由数据中解码得到

Signaling rate 信令速率– Once initialized, each Link must only operate at one of the supported signalinglevels. For the first generation of PCI Express technology, there is only one signaling rate defined, which provides an effective 2.5 Gigabits/second/Lane/direction of raw bandwidth。The data rate is expected to increase with technology advances in the future. 

 Lanes – A Link must support at least one Lane – each Lane represents a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a Link may aggregate multiple Lanes denoted by xN where N may be any of the supported Link widths. An x8 Link represents an aggregate bandwidth of 20 Gigabits/second of raw bandwidth in each direction. This specification describes operations for x1, x2, x4, x8, x12, x16, and x32 Lane widths. 

Initialization– During hardware initialization, each PCI Express Link is set up following a negotiation of Lane widths and frequency of operation by the two agents at each end of the Link.No firmware or operating system software is involved. 

即link的状态与固件和系统软件无关，它根据两者的链路和带宽和时钟来建立的。

Symmetry 对称– Each Link must support a symmetric number of Lanes in each direction, i.e., a x16 Link indicates there are 16 differential signal pairs in each direction. 对称 - 每个连接都要支持在每个方向lane的对称数，也就是说，一个x16链路表示有在每个方向16个差分信号对。