第一章:1.2.3 第四个Verilog程序：function与时序电路组合

此例中原书有错,故进行记录,代码如下:

module MAC #(
    parameter N = 8
    )(
    input   clk,
    input   rstn,
    input   [N-1:0]     opa,
    input   [N-1:0]     opb,
    output  [2*N-1:0]   out
    );
reg     [2*N-1:0]  out_temp;
wire    [2*N-1:0]  sum;
integer cnt;
assign sum = mult(opa,opb)+out_temp;
always @(posedge clk or negedge rstn)begin
    if(!rstn)begin
        out_temp <= 0;
        cnt <= 0;end
    else begin
        out_temp <= sum;
        cnt <= cnt + 1;end
end
assign out = out_temp;

function [2*N-1:0]  mult;
    input   [N-1:0]     opa;
    input   [N-1:0]     opb;
    reg  [2*N-1:0]   result;
    integer i;
begin
    result = opa[0] ? opb:0;
    for(i=1;i<N;i=i+1)begin
        if(opa[i] == 1) result = result + (opb << i);end
    mult = result;
end
endfunction

endmodule

测试代码如下:

module tb(

    );
parameter N = 4;

reg