PCIE6.0学习

目的：记录学习PCIE6.0

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本文为学习PCIE6.0的记录：原文 -> 译文 -> 笔记 -> 理解 -> 总结

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1. Introduction

This chapter presents an overview of the PCI Express architecture and key concepts. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Key attributes, such as usage model, load-store architecture, and software interfaces, are maintained from PCI Local Bus, whereas PCI Local Bus’s parallel bus implementation is replaced by a highly scalable, fully serial interface. PCI Express takes advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality of Service (QoS), Hot-Plug/hot-swap support, data integrity, and error handling are among some of the advanced features supported by PCI Express.

1.1 An Evolving I/O Interconnect

The high-level requirements for this evolving I/O interconnect are as follows:
• Supports multiple market segments and emerging applications:
◦ Unifying I/O architecture for desktop, mobile, workstation, server, communications platforms, and embedded devices
• Ability to deliver low cost, high volume solutions:
◦ Cost at or below PCI cost structure at the system level
• Support multiple platform interconnect usages:
◦ Chip-to-chip, board-to-board via connector or cabling
• A variety of mechanical form factors:
◦ [M.2], [CEM] (Card Electro-Mechanical), [U.2], [OCuLink]
• PCI-compatible software model:
◦ Ability to enumerate and configure PCI Express hardware using PCI system configuration software implementations with no modifications
◦ Ability to boot existing operating systems with no modifications
◦ Ability to support existing I/O device drivers with no modifications
◦ Ability to configure/enable new PCI Express functionality by adopting the PCI configuration paradigm
• Performance:
◦ Low-overhead, low-latency communications to maximize application payload bandwidth and Link efficiency
◦ High-bandwidth per pin to minimize pin count per device and connector interface
◦ Scalable performance via aggregated Lanes and signaling frequency
• Advanced features:
◦ Comprehend different data types and ordering rules
◦ Power management and budgeting
▪ Ability to identify power management capabilities of a Device of a specific Function
▪ Ability to transition a Device or Function into a specific power state
▪ Ability to receive notification of the current power state of a Device of Function
▪ Ability to generate a request to wakeup from a power-off state of the main power supply
▪ Ability to sequence Device power-up to allow graceful platform policy in power budgeting
◦ Ability to support differentiated services, i.e., different (QoS)
▪ Ability to have dedicated Link resources per QoS data flow to improve fabric efficiency and
effective application-level performance in the face of head-of-line blocking
▪ Ability to configure fabric QoS arbitration policies within every component
▪ Ability to tag end-to-end QoS with each packet
▪ Ability to create end-to-end isochronous (time-based, injection rate control) solutions
◦ Hot-Plug support
▪ Ability to support existing PCI Hot-Plug solutions
▪ Ability to support native Hot-Plug solutions (no sideband signals required)
▪ Ability to support async removal
▪ Ability to support a unified software model for all form factors
◦ Data Integrity
▪ Ability to support Link-level data integrity for all types of transaction and Data Link packets
▪ Ability to support end-to-end data integrity for high availability solutions
◦ Error handling
▪ Ability to support PCI-Compatible error handling
▪ Ability to support advanced error reporting and handling to improve fault isolation and
recovery solutions
◦ Process Technology Independence
▪ Ability to support different DC common mode voltages at Transmitter and Receiver
◦ Ease of Testing
▪ Ability to test electrical compliance via simple connection to test equipment

1.2 PCI Express Link

A Link represents a dual-simplex communications channel between two components. The fundamental PCI Express Link consists of two, low-voltage, differentially driven signal pairs: a Transmit pair and a Receive pair as shown in § Figure 1-1 . A PCI Express Link consists of a PCIe PHY as defined in § Chapter 4.

The primary Link attributes for PCI Express Link are:

• The basic Link - PCI Express Link consists of dual unidirectional differential Links, implemented as a Transmit pair and a Receive pair. A data clock is embedded using an encoding scheme (see § Chapter 4. ) to achieve very high data rates.

• The Signaling method – Each major revision of PCI Express signaling has evolved one (or more) characteristics to increase bandwidth. Throughout this specification, the term GT/s is used to refer to the number of encoded bits transferred in a second on a direction of a Lane. The actual effective data rate is dependent on a combination of modulation method, encoding method, and data rate. § Table 1-1 provides a summary of Max Data Rate, Modulation Scheme, Encoding Method, and Effective Max Data Rate with the accounting of only encoding overhead for all the six major revisions of PCI Express. See § Chapter 4. for more information about the combined signaling method and § Chapter 8. for electrical specification details for each major PCI Express revision.
  

    Table 1-1 PCIe Signaling Characteristics
    Data Rate Modulation Encoding Effective Data Rate
    (after removing Encoding overhead)
    Base Specification Revision
    6.x 5.x 4.x 3.0 2.0 1.0
    2.5 GT/s NRZ 8b/10b 2 Gbit/s ✓ ✓ ✓ ✓ ✓ ✓
    5.0 GT/s NRZ 8b/10b 4 Gbit/s ✓ ✓ ✓ ✓ ✓
    8.0 GT/s NRZ 128b/130b ~8 Gbit/s ✓ ✓ ✓ ✓
    16.0 GT/s NRZ 128b/130b ~16 Gbit/s ✓ ✓ ✓
    32.0 GT/s NRZ 128b/130b ~32 Gbit/s ✓ ✓
    64.0 GT/s PAM4 1b/1b 64 Gbit/s ✓
  

• Lanes - A Link must support at least one Lane - each Lane represents a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a Link may aggregate multiple Lanes denoted by xN where N may be any of the supported Link widths. A x8 Link operating at the 2.5 GT/s data rate represents an aggregate bandwidth of 20 Gigabits/second of raw bandwidth in each direction. This specification describes operations for x1, x2, x4, x8, and x16 Lane widths.

• Initialization - During hardware initialization, each PCI Express Link is set up following a negotiation of Lane widths and frequency of operation by the two agents at each end of the Link. No firmware or operating ystem software is involved.

• Symmetry - Each Link must support a symmetric number of Lanes in each direction, i.e., a x16 Link indicates there are 16 differential signal pairs in each direction.

    链路是指两组件之间的一条**双单工**通信通道。一条基本PCIE链路，由两个低电压、差分驱动的信号对：一个发送对，一个接受对，如图1-1所示。一条PCIE链路由第四章定义的一个PCIE物理层构成。
  

	PCIE链路具有以下主要链路特性：
	 - 基本链路——PCIE链路由两个单向差分链路构成，具体实现为一个发送对和一个接受对。数据时钟使用编码方式内嵌在数据中，以实现极高数据速率。
	 - 信号方式：PCI Express信令的每一次重大修订都形成一个（或多个）特性来增加带宽。在本规范中，术语GT/s是用于表示一个通道上在一个方向上每秒传输的编码后的比特个数。实际有效数据速率同时取决于调制方法、编码方法和数据速率。表1-1总结了PCI Express六个主要版本的最大数据速率、调制方案、编码方法和仅考虑编码开销的有效最大数据速率。更多有关组合的信号方式见第四章，有关每个PCI Express版本的电气规格详细信息见第八章。
	 - 通道：一条链路必须至少支持一个通道——每个通道表示一组差分信号对（一对信号用于发送，一对信号用于接收）。为了缩放带宽，一条链路可能由xN多个通道聚合而成，这里的N可以是任何支持的链路宽度。以2.5 GT/s数据速率运行的x8链路在每个方向上的总带宽为20千兆比特/秒的原始带宽。本规范描述了x1、x2、x4、x8和x16通道的操作。
	 - 初始化：在硬件初始化过程中，每个PCIE链路都是在链路两端的代理协商好链路宽度和工作频率之后建立起来。这个过程不涉及固件或操作系统软件。
	 - 对称性：每条link必须支持在每个方向上（组件A->组件B的方向以及组件B->组件A的方向）具有相同个数的lane，即一个x16的link表示在每个方向上由16个差分信号对。

1.3 PCI Express Fabric Topology

A fabric is composed of point-to-point Links that interconnect a set of components - an example fabric topology is shown in § Figure 1-2 . This figure illustrates a single fabric instance with two Hierarchies composed of a Root Complex (RC), multiple Endpoints, and multiple Switches, interconnected via PCI Express Links.

1.3 PCIE拓扑结构
一个结构是由互联了一系列组件的点对点链路组成，一个拓扑结构的示例如1-2所示。这个图展示了单一结构实例，它有两个层次结构，具体由根复合体（RC）、多个终端（EP）和多个交换机（SWITCH）组成，这些组件之间通过PCIE链路实现互联。

1.3.1 Root Complex

• An RC denotes the root of an I/O hierarchy that connects the CPU/memory subsystem to the I/O.
• As illustrated in § Figure 1-2 , an RC may support one or more PCI Express Ports. Each interface defines a separate hierarchy domain. Each hierarchy domain may be composed of a single Endpoint or a sub-hierarchy containing one or more Switch components and Endpoints.
• The capability to route peer-to-peer transactions between hierarchy domains through an RC is optional and implementation dependent. An RC is permitted to “take ownership” of Requests that pass peer-to-peer between Root Ports, reforming and potentially spliting a Request such that it may appear to the ultimate Completer that the RC was the origin of the Request, and subsequently the RC must reform the Completion(s) being returned to the original Requester. Alternately, an RC implementation may incorporate a real or virtual Switch internally within the Root Complex to enable full peer-to-peer support in a software transparent way.

Unlike the rules for a Switch, an RC is generally permitted to split a packet into smaller packets when routing transactions peer-to-peer between hierarchy domains (except as noted below), e.g., split a single packet with a 256-byte payload into two packets of 128 bytes payload each. The resulting packets are subject to the normal packet formation rules contained in this specification (e.g., Max_Payload_Size, Read Completion Boundary (RCB), etc.). Component designers should note that splitting a packet into smaller packets may have negative performance consequences, especially for a transaction addressing a device behind a PCI Express to PCI/PCI-X bridge.

Exception: An RC that supports peer-to-peer routing of Deferrable Memory Write Requests is not permitted to split a Deferrable Memory Write Request packet into smaller packets (see § Section 6.32 ).

Exception: An RC that supports peer-to-peer routing of Vendor_Defined Messages is not permitted to split a Vendor_Defined Message packet into smaller packets except at 128-byte boundaries (i.e., all resulting packets except the last must be an integral multiple of 128 bytes in length) in order to retain the ability to forward the Message across a PCI Express to PCI/PCI-X Bridge.

2. Transaction Layer Specification

2.1 Transaction Layer Overview

At a high level, the key aspects of the Transaction Layer are:

• A pipelined full Split-Transaction protocol
• Mechanisms for differentiating the ordering and processing requirements of Transaction Layer Packets (TLPs)
• Credit-based flow control
• Optional support for data poisoning and end-to-end data integrity detection.

The Transaction Layer comprehends the following:

• TLP construction and processing
• Association of transaction-level mechanisms with device resources including:
  – Flow Control
  – Virtual Channel management
• Rules for ordering and management of TLPs
  – PCI/PCI-X compatible ordering
  – Including Traffic Class differentiation

This chapter specifies the behaviors associated with the Transaction Layer.

2.1.1 Address Spaces, Transaction Types, and Usage

Transactions form the basis for information transfer between a Requester and Completer. Four address spaces are defined, and different Transaction types are defined, each with its own unique intended usage, as shown in § Table 2-1 .

Address Space	Transaction Types	Basic Usage
Memory	Read / Write	Transfer data to/from a memory-mapped location
I/O	Read / Write	Transfer data to/from an I/O-mapped location
Configuration	Read / Write	Device Function configuration/setup
Message	Baseline (including Vendor-Defined)	From event signaling mechanism to general purpose messaging

Details about the rules associated with usage of these address formats and the associated TLP formats are described
later in this chapter.

4. Physical Layer Logical Block

4.1 Introduction

The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data interchange. The Physical Layer is divided into the logical and electrical sub-blocks (see § Figure 4-1 ).

§ Chapter 4. describes the logical sub-block and § Chapter 8. describes the electrical sub-block.

	物理层将事务层和数据链路层与用于链路数据交换的信令技术隔离开来。物理层分为逻辑和电气子层（见图4-1）
	第四章描述了逻辑子层，第八章描述了电气子层。

4.2 Logical Sub-block

The logical sub-block has two main sections: a Transmit section that prepares outgoing information passed from the Data Link Layer for transmission by the electrical sub-block, and a Receiver section that identifies and prepares received information before passing it to the Data Link Layer.

逻辑子层有两个主要部分：	一个传输部分————准备从数据链路层传递出去的信息，以供电气子层传输；	另一个接收器部分————在将接收到的信息传递到数据链路层之前，识别并准备接收到的信息。

The logical sub-block and electrical sub-block coordinate the state of each Transceiver through a status and control register interface or functional equivalent. The logical sub-block directs control and management functions of the Physical Layer.

	逻辑子块和电气子块通过状态和控制寄存器接口或等效功能协调每个收发器的状态.逻辑子块指导物理层的控制和管理功能。

PCI Express uses three types of encoding (8b/10b, 128b/130b, and 1b/1b) and two Data Stream modes (Flit Mode and Non-Flit Mode). A Data Stream in the Non-Flit Mode is defined as a contiguous collection of TLPs, DLLPs, and Logical Idle/IDL Token, starting at the end of an Ordered Set and ending with another Ordered Set or a Link Electrical Idle. A Data Stream in Flit Mode is defined as a set of Flits ⇅↓(defined later),↓ ⇅↕(see § Section 4.2.3 ),↕ starting at the end of the first SKP Ordered Set after an SDS Ordered Set , and ending with the last Flit prior to an Ordered Set other than SKP Ordered Set that causes the Link to exit out of L0 state or if the Link enters Electrical Idle. The encoding is determined by the Data ⇅↓Rate.↓ ⇅↕Rate of the Link.↕ The Data Stream mode is determined during initial Link training if both the Ports (and all Pseudo-Ports, if any) support it. See § Table 4-1 for valid encoding and symbol placement mode combinations.

PCIE使用三种类型的编码方式（8b/10b、128b/130b和1b/1b）和两种数据流模式（Flit模式和Non-Flit模式）。Non-Flit模式下的数据流被定义为TLPs、DLLPs和Logical Idle/IDL的连续集合，从有序集的末尾开始，以后接另一个有序集或链路电空闲结束。Flit模式下的数据流被定义为一组Flits(参见§4.2.3)，从SDS有序集之后的第一个SKP有序集的末尾开始，到SKP之外的有序集之前的最后一个Flit结束，该有序集会导致链路退出L0状态或链路进入电空闲状态。编码方式由链路的数据速率决定。如果两个端口(和所有伪端口，如果有的话)都支持该数据流模式，则在初始链路训练期间确定数据流模式。有效的编码和符号放置模式组合参见§表4-1。

Table 4-1 Valid Encoding and Data Stream Mode Combinations

Current Data Rate	Flit Mode Negotiated during Configuration when LinkUp=0b	Encoding	Data Stream
2.5 GT/s, 5.0 GT/s	No	8b/10b	Non-Flit Mode
2.5 GT/s, 5.0 GT/s	Yes	8b/10b	Flit Mode
8.0 GT/s, 16.0 GT/s, 32.0 GT/s	No	128b/130b	Non-Flit Mode
8.0 GT/s,16.0 GT/s, 32.0 GT/s	Yes	128b/130b	Flit Mode
64.0 GT/s	Yes(mandatory)	1b/1b	Flit Mode

The Ordered Set encoding follows the 8b/10b, 128b/130b, and 1b/1b encoding as defined in § Table 4-2.

Table 4-2 Valid Encoding for Ordered Sets

Current Data Rate	Flit Mode Negotiated during Configuration when LinkUp=0b	Encoding	Comments
2.5 GT/s, 5.0 GT/s	Yes/No	8b/10b	Same Ordered Sets are used in Flit Mode as well as Non-Flit Mode.
8.0 GT/s	No	128b/130b	Only Standard SKP Ordered Set sent when SKP OS needs to be sent. Rest of the Ordered Sets are identical for Non-Flit Mode and Flit Mode in 8.0 GT/s.
16.0 GT/s, 32.0 GT/s	No	128b/130b	Alternates between Standard SKP OS and Control SKP OS, when SKP OS needs to be sent. Rest of the Ordered Sets are identical for Non-Flit Mode and Flit Mode in the corresponding Data Rate.
8.0 GT/s,16.0 GT/s, 32.0 GT/s	Yes	128b/130b	Alternates between Standard SKP OS and Control SKP OS, when SKP OS needs to be sent. Rest of the Ordered Sets are identical for Non-Flit Mode and Flit Mode in the corresponding Data Rate.
64.0 GT/s	Yes(mandatory)	1b/1b	All Ordered Sets follow 1b/1b encoding at 64.0 GT/s with PAM4 signaling. Only Control SKP OS sent when SKP OS needs to be sent.

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**IMPLEMENTATION NOTE: FLIT MODE IDENTIFICATION THROUGHOUT THE DOCUMENT** Support for Flit Mode behavior is referenced five times in the specification through the use of the following fields/variables: Flit Mode Supported bit Bit 0 of the Data Rate Identifier Symbol of 8b/10b and 128b/130b encoded TS1s and TS2s. This bit is Set when the Flit Mode Supported bit in the PCI Express Capabilities Register is Set and the Flit Mode Disable bit in the Link Control Register is Clear. See § Table 4-25, § Table 4-26, and § Table 4-27. Flit_Mode_Enabled Variable that indicates whether or not Flit Mode has been sucesfully negotiated. See § Section 4.2.7.1.1 and§ Section 4.2.7.3.2 . Flit Mode Supported Field in the PCI Express Capabilities Register. Flit Mode is supported when this bit is Set. See § Section 7.5.3.2. Flit Mode Disable Field in the Link Control Register. This bit used to disable Flit Mode. This bit is most useful in Downstream Ports but is also defined for Upstream Ports (useful for crosslinks or by device firmware). See § Section 7.5.3.7 . Setting this bit may be useful to workaround faulty hardware. Flit Mode Status Field in the Link Status 2 Register. Indicates that that the Link is or will be operating in Flit Mode. Should match the Flit_Mode_Enabled variable. See § Section 7.5.3.20 .

4.2.1 8b/10b Encoding for 2.5 GT/s and 5.0 GT/s Data Rates

4.2.1.1 Symbol Encoding

At 2.5 and 5.0 GT/s, PCI Express uses an 8b/10b transmission code. The definition of this transmission code is identical to that specified in ANSI X3.230-1994, clause 11 (and also IEEE 802.3z, 36.2.4). Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to encode one of the 12 Special Symbols included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit Symbol. As shown in § Figure 4-2, ABCDE maps to abcdei and FGH maps to fghj.

4.2.1.1.1 Serialization and De-serialization of Data

The bits of a Symbol are placed on a Lane starting with bit “a” and ending with bit “j”. Examples are shown in § Figure 4-3 and § Figure 4-4.

4.2.1.1.2 Special Symbols for Framing and Link Management (K Codes)

The 8b/10b encoding scheme provides Special Symbols that are distinct from the Data Symbols used to represent Characters. These Special Symbols are used for various Link Management mechanisms described later in this chapter. Special Symbols are also used to frame DLLPs and TLPs 59 in Non-Flit Mode, using distinct Special Symbols to allow these two types of Packets to be quickly and easily distinguished. When Flit Mode is enabled, each Symbol (Byte) of the Data Stream is still encoded with 8b/10b encoding without the Framing described. The Flit Mode operation is described in § Section 4.2.3.1 . Even when Flit Mode is enabled, the Ordered Sets follow the description provided in § Section 4.2.1 , when operating in 2.5 GT/s or 5.0 GT/s Data Rates.

§ Table 4-3 shows the Special Symbols used for PCI Express and provides a brief description for each. These Symbols will be discussed in greater detail in following sections. Each of these Special Symbols, as well as the data Symbols, must be interpreted by looking at the 10-bit Symbol in its entirety.

4.2.1.1.3 8b/10b Decode Rules

The Symbol tables for the valid 8b/10b codes are given in Appendix B. These tables have one column for the positive disparity and one column for the negative disparity.

A Transmitter is permitted to pick any disparity, unless otherwise required, when first transmitting differential data after being in an Electrical Idle state. The Transmitter must then follow proper 8b/10b encoding rules until the next Electrical Idle state is entered.

The initial disparity for a Receiver that detects an exit from Electrical Idle is set to the disparity of the first Symbol used to obtain Symbol lock. Disparity may also be re-initialized if Symbol lock is lost and regained during the transmission of differential information due to an implementation specific number of errors. All following received Symbols after the initial disparity is set must be found in the proper column corresponding to the current running disparity.

If a received Symbol is found in the column corresponding to the incorrect running disparity or if the Symbol does not correspond to either column, the Physical Layer must notify the Data Link Layer that the received Symbol is invalid. This is a Receiver Error, and is a reported error associated with the Port (see § Section 6.2 ) in Non-Flit Mode. In Flit Mode, the Symbol in error is passed to the FEC logic to correct; the Receiver is permitted to send any 8-bit value to the FEC logic if an 8b/10b error or k-char is detected inside the Flit boundary.

4.2.1.2 Framing and Application of Symbols to Lanes

There are two classes of framing and application of Symbols to Lanes. The first class consists of the Ordered Sets. The second class consists of TLPs and DLLPs in the Data Stream. Ordered Sets are always transmitted serially on each Lane, such that a full Ordered Set appears simultaneously on all Lanes of a multi-Lane Link. The Non-Flit Mode of Data Stream is described below. The Flit Mode description for Data Stream is described in § Section 4.2.3.2 and § Section 4.2.3.3 . There are no defined framing-related errors while using 8b/10b encoding in Flit Mode.

4.2.1.2.1 Framing and Application of Symbols to Lanes for TLPs and DLLPs in Non-Flit Mode

The Framing mechanism uses Special Symbol K28.2 “SDP” to start a DLLP and Special Symbol K27.7 “STP” to start a TLP. The Special Symbol K29.7 “END” is used to mark the end of either a TLP or a DLLP.
The conceptual stream of Symbols must be mapped from its internal representation, which is implementation dependent, onto the external Lanes. The Symbols are mapped onto the Lanes such that the first Symbol (representing Character 0) is placed onto Lane 0; the second is placed onto Lane 1; etc. The x1 Link represents a degenerate case and the mapping is trivial, with all Symbols placed onto the single Lane in order.

When no packet information or special Ordered Sets are being transmitted, the Transmitter is in the Logical Idle state. During this time idle data must be transmitted. The idle data must consist of the data byte 0 (00h), scrambled according to the rules of § Section 4.2.1.3 and 8b/10b encoded according to the rules of § Section 4.2.1.1 , in the same way that TLP and DLLP Data Symbols are scrambled and encoded. Likewise, when the Receiver is not receiving any packet information or special Ordered Sets, the Receiver is in Logical Idle and shall receive idle data as described above. During transmission of the idle data, the SKP Ordered Set must continue to be transmitted as specified in § Section 4.2.8 .

For the following rules, “placed” is defined to mean a requirement on the Transmitter to put the Symbol into the proper Lane of a Link.

• TLPs must be framed by placing an STP Symbol at the start of the TLP and an END Symbol or EDB Symbol at the end of the TLP (see § Figure 4-5).
• A properly formed TLP contains a minimum of 18 symbols between the STP and END or EDB Symbols. If a received sequence has less than 18 symbols between the STP and END or EDB symbols, the receiver is permitted to treat this as a Receiver Error.
  • If checked, this is a reported error associated with the Receiving Port (see § Section 6.2 ).
• DLLPs must be framed by placing an SDP Symbol at the start of the DLLP and an END Symbol at the end of the DLLP (see § Figure 4-6).
• Logical Idle is defined to be a period of one or more Symbol Times when no information: TLPs, DLLPs or any type of Special Symbol is being Transmitted/Received. Unlike Electrical Idle, during Logical Idle the Idle data Symbol (00h) is being transmitted and received.
  • When the Transmitter is in Logical Idle, the Idle data Symbol (00h) shall be transmitted on all Lanes. This is scrambled according to the rules in § Section 4.2.1.3 .
  • Receivers must ignore incoming Idle data Symbols, and must not have any dependency other than scramble sequencing on any specific data patterns.
• For Links wider than x1, the STP Symbol (representing the start of a TLP) must be placed in Lane 0 when starting Transmission of a TLP from a Logical Idle Link condition.
• For Links wider than x1, the SDP Symbol (representing the start of a DLLP) must be placed in Lane 0 when starting Transmission of a DLLP from a Logical Idle Link condition.
• The STP Symbol must not be placed on the Link more frequently than once per Symbol Time.
• The SDP Symbol must not be placed on the Link more frequently than once per Symbol Time.
• As long as the above rules are satisfied, TLP and DLLP Transmissions are permitted to follow each other successively.
• One STP Symbol and one SDP Symbol may be placed on the Link in the same Symbol Time.
  • Links wider than x4 can have STP and SDP Symbols placed in Lane 4*N, where N is a positive integer. For example, for x8, STP and SDP Symbols can be placed in Lanes 0 and 4; and for x16, STP and SDP Symbols can be placed in Lanes 0, 4, 8, or 12.
• For xN Links where N is 8 or more, if an END or EDB Symbol is placed in a Lane K, where K does not equal N-1, and is not followed by an STP or SDP Symbol in Lane K+1 (i.e., there is no TLP or DLLP immediately following), then PAD Symbols must be placed in Lanes K+1 to Lane N-1.
  • For example, on a x8 Link, if END or EDB is placed in Lane 3, PAD must be placed in Lanes 4 to 7, when not followed by STP or SDP.
• The EDB Symbol is used to mark the end of a nullified TLP. Refer to § Section 3.6.2.1 for information on the usage of EDB.
• Receivers may optionally check for violations of the rules of this section. These checks are independently optional (see § Section 6.2.3.4 ). If checked, violations are Receiver Errors, and are reported errors associated with the Port (see § Section 6.2 ).

4.2.1.3 Data Scrambling

In order to improve electrical characteristics of a Link, data is typically scrambled. This is applicable for both the Flit Mode as well as Non-Flit Mode at 2.5 GT/s and 5.0 GT/s Data Rates. This involves XORing the data stream with a pattern generated by a Linear Feedback Shift Register (LFSR). On the Transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the Receive side, de-scrambling is applied to characters after 8b/10b decoding.

On a multi-Lane Link, the scrambling function can be implemented with one or many LFSRs. When there is more than one Transmit LFSR per Link, these must operate in concert, maintaining the same simultaneous (Lane-to-Lane Output Skew) value in each LFSR. When there is more than one Receive LFSR per Link, these must operate in concert, maintaining the same simultaneous (Lane-to-Lane Skew) value in each LFSR. Regardless of how they are implemented, LFSRs must interact with data on a Lane-by-Lane basis as if there was a separate LFSR as described here for each Lane within that Link.

The LFSR is graphically represented in § Figure 4-10. Scrambling or unscrambling is performed by serially XORing the 8-bit (D0-D7) character with the 16-bit (D0-D15) output of the LFSR. An output of the LFSR, D15, is XORed with D0 of the data to be processed. The LFSR and data register are then serially advanced and the output processing is repeated for D1 through D7. The LFSR is advanced after the data is XORed. The LFSR implements the polynomial:

G(X)=X^16+X5+X^4+X3+1

The mechanism(s) and/or interface(s) utilized by the Data Link Layer to notify the Physical Layer to disable scrambling is implementation specific and beyond the scope of this specification.

The data scrambling rules are the following:

• The COM Symbol initializes the LFSR.
• The LFSR value is advanced eight serial shifts for each Symbol except the SKP.
• All data Symbols (D codes) except those within Ordered Sets (e.g., TS1, TS2, EIEOS), the Compliance Pattern (see § Section 4.2.9 ), and the Modified Compliance Pattern (see § Section 4.2.10 ) are scrambled.
• All special Symbols (K codes) are not scrambled.
• The initialized value of an LFSR seed (D0-D15) is FFFFh. Immediately after a COM exits the Transmit LFSR, the LFSR on the Transmit side is initialized. Every time a COM enters the Receive LFSR on any Lane of that Link, the LFSR on the Receive side is initialized.
• Scrambling can only be disabled at the end of Configuration (see § Section 4.2.7.3.5 ).
• Scrambling does not apply to a Loopback Follower.
• Scrambling is always enabled in Detect by default.

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IMPLEMENTATION NOTE: DISABLING SCRAMBLING
Disabling scrambling is intended to help simplify test and debug equipment. Control of the exact data patterns is useful in a test and debug environment. Since scrambling is reset at the Physical Layer there is no reasonable way to reliably control the state of the data transitions through software. Thus, the Disable Scrambling bit in the TS1 and TS2 Ordered Sets is provided for these purposes.
The mechanism(s) and/or interface(s) utilized by the Data Link Layer to notify the Physical Layer to disable scrambling is implementation specific and beyond the scope of this specification.

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For more information on scrambling, see § Appendix C. .

4.2.2 128b/130b Encoding for 8.0 GT/s, 16.0 GT/s, and 32.0 GT/s Data Rates

When a PCI Express Link is operating at a data rate of 8.0 GT/s, 16.0 GT/s, or 32.0 GT/s, it uses the 128b/130b encoding rules described in this section. For backwards compatibility, the Link initially trains to L0 at the 2.5 GT/s data rate using 8b/10b encoding as described in § Section 4.2.1 , then when the data rate is changed to 8.0 GT/s, 16.0 GT/s, or 32.0 GT/s, 128b/130b encoding is used. 128b/130b encoding uses a Link-wide packetization mechanism in Non-Flit Mode and a per-Lane block code with scrambling in both Flit Mode and Non-Flit Modes. In the Flit Mode, the Data Stream follows the same mechanism described in § Section 4.2.3.1 , for the 128b payload inside the 128b/130b Data Block(s).

The basic entity of data transmission is an 8-bit data character, referred to as a Symbol, as shown in § Figure 4-11 and § Figure 4-12.

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IMPLEMENTATION NOTE: SYMBOL IN 128B/130B ENCODING SCHEME
In the 128b/130b encoding scheme, the Symbol is one byte long, similar to the 10-bit Symbol of 8b/10b encoding.

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4.2.2.1 Lane Level Encoding

The Physical Layer uses a per-Lane block code. Each Block consists of a 2-bit Sync Header and a payload. There are two valid Sync Header encodings: 10b and 01b. The Sync Header defines the type of payload that the Block contains.

A Sync Header of 10b indicates a Data Block. Each Data Block has a 128 bit payload, resulting in a Block size of 130 bits. The payload is a Data Stream described in § Section 4.2.2.3 .

A Sync Header of 01b indicates an Ordered Set Block. Each Ordered Set Block has a 128 bit payload, resulting in a Block size of 130 bits except for the SKP Ordered Set which can be of variable length.
All Lanes of a multi-Lane Link must transmit Blocks with the same Sync Header simultaneously, except when transmitting Jitter Measurement Pattern in Polling.Compliance.

The bit transmission order is as follows. A Sync Header represented as ‘H1H0’ is placed on a Lane starting with ‘H0’ and ending with ‘H1’. A Symbol, represented as ‘S7S6S5S4S3S2S1S0’, is placed on a Lane starting with ‘S0’ and ending with ‘S7’. In the diagrams that show a time scale, bits represent the transmission order. In layout diagrams, bits are arranged in little-endian format, consistent with packet layout diagrams in other chapters of this specification.

4.2.2.2 Ordered Set Blocks

An Ordered Set Block contains a Sync Header followed by one Ordered Set. All Lanes of a multi-Lane Link must transmit the same Ordered Set type simultaneously. The first Symbol of the Ordered Set defines the type of Ordered Set. Subsequent symbols of the Ordered Set are defined by the Ordered Set type and need not be identical across lanes of a multi-Lane Link. The Ordered Sets are described in detail in § Section 4.2.5 and § Section 4.2.8 . Ordered Set Blocks are the same for both Flit Mode and Non-Flit Mode except for the use and frequency of SKP Ordered Set. In Flit Mode at 8.0 GT/s, both Standard SKP Ordered Sets and Control SKP Ordered Sets are used.

4.2.2.2.1 Block Alignment

During Link training, the 130 bits of the Electrical Idle Exit Ordered Set (EIEOS) are a unique bit pattern that Receivers use to determine the location of the Block Sync Headers in the received bit stream. Conceptually, Receivers can be in three different phases of Block alignment: Unaligned, Aligned, and Locked. These phases are defined to illustrate the required behavior, but are not meant to specify a required implementation.

Unaligned Phase
Receivers enter this phase after a period of Electrical Idle, such as when the data rate is changed to one that uses 128b/130b encoding or when they exit a low-power Link state, or if directed (by an implementation specific method). In this phase, Receivers monitor the received bit stream for the EIEOS bit pattern. When one is detected, they adjust their alignment to it and proceed to the Aligned phase.

Aligned Phase
Receivers monitor the received bit stream for the EIEOS bit pattern and the received Blocks for a Start of Data Stream (SDS) Ordered Set. If an EIEOS bit pattern is detected on an alignment that does not match the current alignment, Receivers must adjust their alignment to the newly received EIEOS bit pattern. If an SDS Ordered Set is received, Receivers proceed to the Locked phase. Receivers are permitted to return to the Unaligned phase if an undefined Sync Header (00b or 11b) is received.

Locked Phase
Receivers must not adjust their Block alignment while in this phase. The Data Stream starts after an SDS Ordered Set, and adjusting the Block alignment would interfere with the processing of these Blocks. Receivers must return to the Unaligned or Aligned phase if an undefined Sync Header is received.

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IMPLEMENTATION NOTE:DETECTION OF LOSS OF BLOCK ALIGNMENT
The sequence of EIEOS and TS Ordered Sets transmitted during training sequences will cause misaligned Receivers to detect an undefined Sync Header.

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Additional Requirements:

• While in the Aligned or Locked phase, Receivers must adjust their alignment as necessary when a SKP Ordered Set is received. See § Section 4.2.8 for more information on SKP Ordered Sets.
• After any LTSSM transition to Recovery, Receivers must ignore all received TS Ordered Sets until they receive an EIEOS. Conceptually, receiving an EIEOS validates the Receiver’s alignment and allows TS Ordered Set processing to proceed. If a received EIEOS initiates an LTSSM transition from L0 to Recovery, Receivers are permitted to process any TS Ordered Sets that follow the EIEOS or ignore them until another EIEOS is received after entering Recovery.
• Receivers are permitted to transition from the Locked phase to the Unaligned or Aligned phase as long as Data Stream processing is stopped. See § Section 4.2.2.3 for more information on Data Stream requirements.
• Loopback Leads: While in Loopback.Entry, Leads must be capable of adjusting their Receiver’s Block alignment to received EIEOS bit patterns. While in Loopback.Active, Leads are permitted to transmit an EIEOS and adjust their Receiver’s Block alignment to the looped back bit stream.
• Loopback Followers: While in Loopback.Entry, Followers must be capable of adjusting their Receiver’s Block alignment to received EIEOS bit patterns. While in Loopback.Active, Followers must not adjust their Receiver’s Block alignment. Conceptually, the Receiver is directed to the Locked phase when the Follower starts to loop back the received bit stream.

4.2.2.3 Data Blocks

The payload of Data Blocks is a stream of Symbols defined as a “Data Stream”. In Non-Flit Mode, the Data Stream consists of Framing Tokens, TLPs, and DLLPs. In Flit Mode, the Data Stream is described in § Section 4.2.3.1 . Each Symbol of the Data Stream is placed on a single Lane of the Link, and the stream of Symbols is striped across all Lanes of the Link and spans Block boundaries.

A Data Stream starts with the first Symbol of the Data Block that follows an SDS Ordered Set. It ends either when a Framing Error is detected or with the last Symbol of the Data Block that precedes an Ordered Set other than a SKP Ordered Set. SKP Ordered Sets that occur within a Data Stream have specific requirements as described in the following sections.

4.2.2.3.1 Framing Tokens in Non-Flit-Mode

The Framing Tokens used by the Physical Layer in Non-Flit Mode are shown in § Table 4-4. Each Framing Token specifies or implies the number of Symbols associated with the Token and therefore the location of the next Framing Token. § Figure 4-15 shows an example of TLPs, DLLPs, and IDLs transmitted on a x8 link.

The first Framing Token of a Data Stream is always located in Symbol 0 of Lane 0 of the first Data Block of the Data Stream. For the rest of this chapter, the terms Framing Token and Token are used interchangeably.

Table 4-4 Framing Token Encoding

Framing Token Type	Description
IDL	Logical Idle. The Framing Token is 1 Symbol. This Token is transmitted when no TLPs or DLLPs or other Framing Tokens are being transmitted.
SDP	Start of DLLP. The Framing Token is 2 Symbols long and is followed by the DLLP information.
STP	Start of TLP. The Framing Token is 4 Symbols long and includes the 12-bit TLP Sequence Number. It is followed by the TLP information.
EDB	EnD Bad. The Framing Token is 4 Symbols long and is used to confirm that the previous TLP was nullified.
EDS	End of Data Stream. The Framing Token is four Symbols long and indicates that the next Block will be an Ordered Set Block.

The Physical Layer DLLP layout is shown in § Figure 4-14. Symbols 0 and 1 are the SDP Token, and Symbols 2 through 7 are the Data Link Layer DLLP information. The Physical Layer TLP layout is shown in § Figure 4-14. Details of the STP Framing Token are shown in § Figure 4-13. The length of the TLP (in DWs) being transmitted is specified by an 11-bit field called TLP Length. The TLP Length field is the total amount of information transferred, including the Framing Token, TLP Prefixes (if any), TLP Header, TLP data payload (if any), TLP digest (if any), TLP PCRC (if any), TLP MAC (if any), and TLP LCRC. For example, if a TLP has a 3 DW header, a 1 DW data payload, and does not include a TLP digest, the TLP Length field value is 6: 1 (Framing Token) + 0 (TLP Prefixes) + 3 (TLP header) + 1 (TLP data payload) + 0 (TLP digest) + 1 (TLP LCRC). If the same TLP included a TLP digest, the TLP Length field value would be 7. When a TLP is nullified, the EDB Token is considered an extension of the TLP but is not included in the calculation of the TLP Length field.

The TLP Length field is protected by a 4-bit CRC (Frame CRC), and an even parity bit (Frame Parity) protects both the TLP Length and Frame CRC fields. The Frame CRC and Frame Parity are calculated as follows:

C[0] = L[10] ^ L[7] ^ L[6] ^ L[4] ^ L[2] ^ L[1] ^ L[0]
C[1] = L[10] ^ L[9] ^ L[7] ^ L[5] ^ L[4] ^ L[3] ^ L[2]
C[2] = L[9] ^ L[8] ^ L[6] ^ L[4] ^ L[3] ^ L[2] ^ L[1]
C[3] = L[8] ^ L[7] ^ L[5] ^ L[3] ^ L[2] ^ L[1] ^ L[0]
P = L[10] ^ L[9] ^ L[8] ^ L[7] ^ L[6] ^ L[5] ^ L[4] ^ L[3] ^ L[2] ^ L[1] ^ L[0] ^ C[3] ^ C[2] ^ C[1] ^ C[0]

The Frame Parity reduces to P = L[10] ^ L[9] ^ L[8] ^ L[6] ^ L[5] ^ L[2] ^ L[0]

The TLP Length field is represented in the above equations as L[10:0], where L[0] is the least significant bit and L[10] is the most significant bit. Transmitters calculate the Frame CRC and Frame Parity before transmission. Receivers must calculate the Frame CRC and Frame Parity using the same algorithm as the transmitter and then compare the calculated values to the received values.

STP Tokens do not have a TLP Length field value of 1. If a received sequence of Symbols matches the format of an STP Token with a TLP Length field value of 1, the Symbols are evaluated to determine whether they match the EDS Token.

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IMPLEMENTATION NOTE: FRAME CRC AND FRAME PARITY
The Frame CRC bits are effectively calculated as (L[0] X14 + L[1] X13 + … + L[9] X5 + L[10] X4) mod (X4 + X +1). It should be noted that X4 + X + 1 is a primitive polynomial and the CRC can detect two bit errors. The Frame Parity bit can detect an odd number of bit errors. Thus, the Frame CRC and Frame Parity together guarantee three bit error detection for the TLP Length field. It must be noted that even though in the reduced Frame Parity equation all terms are not present, it still maintains the property of detecting odd bit errors. Only those TLP Length field bits which are present in an even number of CRC terms are used in the calculation.

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Note that, for TLPs, the Data Link Layer prepends 4 Reserved bits (0000b) to the TLP Sequence Number field before it calculates the LCRC. These Reserved bits are not explicitly transmitted when using 128b/130b encoding, and Receivers assume that the 4 bits received are 0000b when calculating the LCRC.

Packets containing a TLP Length field that is greater than 1535 are PMUX Packets. For such packets, the actual packet length is computed differently, the TLP Sequence Number field in the STP Token contains other information, and the Link CRC is computed using different rules. See § Appendix G. for details.
Packets containing a TLP Length field that is between 1152 and 1535 (inclusive) are reserved for future standardization.

Transmitters must transmit all DWs of a TLP specified by the TLP Length field of the STP Framing Token. TLPs are never truncated when using 128b/130b encoding - even when nullified. § Figure 4-16 shows an example of a nullified 23 DW TLP.

§ Figure 4-17 shows an example of TLPs, DLLPs, IDLs, and an EDS Token followed by a SKP Ordered Set. SKP Ordered Sets are defined in § Section 4.2.8.2 .

4.2.2.3.2 Transmitter Framing Requirements in Non-Flit Mode

The following requirements apply to the transmitted Data Stream.

• To Transmit a TLP:
  • Transmit an STP Token immediately followed by the complete TLP information provided by the Data Link Layer.
  • All DWs of the TLP, as specified by the TLP Length field of the STP Token, must be transmitted, even if the TLP is nullified.
  • If the TLP is nullified, an EDB Token must be transmitted immediately following the TLP. There must be no Symbols between the last Symbol of the TLP and the first Symbol of the EDB Token. The value of the TLP Length field of a nullified TLP’s STP Token is not adjusted to account for the EDB Token.
  • The STP Token must not be transmitted more frequently than once per Symbol Time.
• To Transmit a DLLP:
  • Transmit an SDP Token immediately followed by the complete DLLP information provided by the Data Link Layer.
  • All 6 Symbols of the DLLP must be transmitted.
  • The SDP Token must not be transmitted more frequently than once per Symbol Time.
• To Transmit a SKP Ordered Set within a Data Stream:
  • Transmit an EDS Token in the last DW of the current Data Block. For example, the Token is transmitted on Lane 0 in Symbol Times 12-15 of the Block for a x1 Link, and on Lanes 12-15 of Symbol Time 15 of the Block for a x16 Link.
  • Transmit the SKP Ordered Set following the current Data Block.
  • Transmit a Data Block following the SKP Ordered Set. The Data Stream resumes with the first Symbol of the Data Block. If multiple SKP Ordered Sets are scheduled for transmission, each SKP Ordered Set must be preceded by a Data Block with an EDS Token.
• To end a Data Stream:
  • Transmit an EDS Token in the last DW of the current Data Block, followed in the next block by an EIOS or an EIEOS. An EIOS is transmitted for LTSSM power management state transitions, and an EIEOS is transmitted for all other cases. For example, the Token is transmitted on Lane 0 in Symbol Times 12-15 of the Block for a x1 Link, and on Lanes 12-15 of Symbol Time 15 of the Block for a x16 Link.
• The IDL Token must be transmitted on all Lanes when not transmitting a TLP, DLLP, or other Framing Token.
• Multi-Lane Links:
  • After transmitting an IDL Token, the first Symbol of the next STP or SDP Token must be transmitted in Lane 0 of a future Symbol Time. An EDS Token can be transmitted after an IDL Token in the same Symbol Time, since it must be transmitted in the last DW of a Block.
  • For xN Links where N is 8 or more, if an EDB Token, TLP, or DLLP ends in a Lane K, where K does not equal N-1, and it is not followed by the first Symbol of an STP, SDP, or EDB Token in Lane K+1, then IDL Tokens must be placed in Lanes K+1 to N-1. For example, on a x8 Link, if a TLP or DLLP ends in Lane 3, IDL Tokens must be placed in Lanes 4 to 7. The EDS Token is an exception to this requirement, and can be transmitted following IDL Tokens.
  • Tokens, TLPs, and DLLPs are permitted to follow each other successively such that more than one Token may be transmitted in the same Symbol Time as long as their transmission conforms with the other requirements stated in this section.
    • Links wider than x4 can have Tokens placed starting on Lane 4*N, where N is a positive integer. For example, Tokens can be placed in Lanes 0 and 4 of a x8 Link, and Tokens can be placed in Lanes 0, 4, 8, or 12 of a x16 Link.

4.2.2.3.3 Receiver Framing Requirements in Non-Flit Mode

The following requirements apply to the received Data Stream and the Block type transitions that occur at the beginning and end of the Data Stream.

• When processing Symbols that are expected to be a Framing Token, receiving a Symbol or sequence of Symbols that does not match the definition of a Framing Token is a Framing Error. It is strongly recommended that Receivers of a multi-Lane Link report an error in the Lane Error Status Register for the Lane that receives the first Symbol of an expected Framing Token when that Symbol does not match Symbol +0 of an STP (bits [3:0] only), IDL, SDP, EDB, or EDS Token (see § Figure 4-13).
• All optional error checks and error reports in this section are independently optional (see § Section 6.2.3.4 ).
• When an STP Token is received:
  • Receivers must calculate the Frame CRC and Frame Parity of the received TLP Length field and compare the results to the received Frame CRC and Frame Parity fields. A Frame CRC or Frame Parity mismatch is a Framing Error.
    • An STP Token with Framing Error is not considered part of a TLP for the purpose of reporting to the Data Link Layer.
  • If the TLP Length field is 1, the Symbols are not an STP Token and are instead evaluated to determine whether they are an EDS Token.
  • Receivers are permitted to check whether the TLP Length field has a value of 0. If checked, receiving a TLP Length field of 0 is a Framing Error.
  • Receivers are permitted to check whether the TLP Length field has a value of 2, 3, or 4. If checked, eceiving such a TLP Length field is a Framing Error.
  • Receivers are permitted to check whether the TLP Length field has a value between 1152 and 1535 (inclusive). If checked, receiving such a TLP Length field is a Framing Error.
  • Receivers on Ports that do not support Protocol Multiplexing are permitted to check whether the TLP Length field has a value greater than 1535. If checked, receiving such a TLP Length field is a Framing Error.
  • Receivers on Ports that support Protocol Multiplexing, shall process STP Tokens with a TLP Length field that is greater than 1535 as the start of a PMUX Packet as defined in § Appendix G. .
  • The next Token to be processed begins with the Symbol immediately following the last DW of the TLP, as determined by the TLP Length field.
    • Receivers must evaluate this Symbol and determine whether it is the first Symbol of an EDB Token and therefore whether the TLP is nullified. See the EDB Token requirements.
  • Receivers are permitted to check whether more than one STP Token is received in a single Symbol Time. If checked, receiving more than one STP Token in a single Symbol Time is a Framing Error
• When an EDB Token is received:
  • If an EDB Token is received immediately following a TLP (there are no Symbols between the last Symbol of the TLP and the first Symbol of the EDB Token), receivers must inform the Data Link Layer that an EDB Token has been received. Receivers are permitted to inform the Data Link Layer that an EDB Token has been received after processing the first Symbol of the EDB Token or after processing any or all of the remaining Symbols of the EDB Token. Regardless of when they inform the Data Link Layer of a received EDB Token, Receivers must check all Symbols of the EDB Token. Receiving a Symbol that does not match the definition of an EDB Token is a Framing Error.
  • Receiving an EDB Token at any time other than immediately following a TLP is a Framing Error.
  • The next Token to be processed begins with the Symbol immediately following the EDB Token.
• When an EDS Token is received in the last four Symbols of the Data Block across the Link:
  • Receivers must stop processing the Data Stream.
  • Receiving an Ordered Set other than SKP, EIOS, or EIEOS in the Block following the EDS Token is a Framing Error.
  • If a SKP Ordered Set is received in the Block following the EDS Token, Receivers resume Data Stream processing with the first Symbol of the Data Block that follows the SKP Ordered Set unless a Framing Error has been detected.
• When an SDP Token is received:
  • The next Token to be processed begins with the Symbol immediately following the last Symbol of the DLLP.
  • Receivers are permitted to check whether more than one SDP Token is received in a single Symbol Time. If checked, receiving more than one SDP Token in a single Symbol Time is a Framing Error.
• When an IDL Token is received:
  • For a x1 Link, the next Token to be processed begins with the next Symbol received.
  • For a x2 Link, the next Token to be processed begins with the Symbol received in Lane 0 of the next Symbol Time. It is strongly recommended that Receivers check whether the Symbol received in Lane 1, if it did not receive IDL, after an IDL Token was received in Lane 0 is also IDL and report an error for Lane 1 in the Lane Error Status Register. If checked, receiving a Symbol other than IDL is a Framing Error.
  • For a x4 Link, the next Token to be processed begins with the Symbol received in Lane 0 of the next Symbol Time. It is strongly recommended that Receivers check whether the Symbols received in Lanes 1-3, after an IDL Token was received in Lane 0 are also IDL and report an error for the Lane(s) that did not receive IDL, in the Lane Error Status Register. If checked, receiving a Symbol other than IDL is a Framing Error.
  • For x8 and x16 Links, the next Token to be processed begins with the Symbol received in the next DW aligned Lane following the IDL Token. For example, if an IDL Token is received in Lane 4 of a x16 Link, the next Token location begins with Lane 8 of the same Symbol Time. However, if an IDL Token is received on Lane 4 of a x8 Link, the next Token location begins with Lane 0 of the following Symbol Time. It is strongly recommended that Receivers check whether the Symbols received between the IDL Token and the next Token location are also IDL and report an error for the Lane(s) that did not receive IDL, in the Lane Error Status Register. If checked, receiving a Symbol other than IDL is a Framing Error.
    Note: The only Tokens expected to be received in the same Symbol Time following an IDL Token are additional IDL Tokens or an EDS Token.
• While processing the Data Stream, Receivers must also check the Block type received by each Lane, after accounting for Lane-to-Lane de-skew, for the following conditions:
  • Receiving an Ordered Set Block on any Lane immediately following an SDS Ordered Set is a Framing Error.
  • Receiving a Block with an undefined Block type (a Sync Header of 11b or 00b) is a Framing Error. It is strongly recommended that Receivers of a multi-Lane Link report an error for any Lane that received the undefined Block type in the Lane Error Status register.
  • Receiving an Ordered Set Block on any Lane without receiving an EDS Token in the preceding Block is a Framing Error. For example, receiving a SKP Ordered Set without a preceding EDS Token is a Framing Error. In addition, receiving a SKP Ordered Set followed immediately by another Ordered Set Block (including another SKP Ordered Set) within a Data Stream is a Framing Error. It is strongly recommended that if the first Symbol of the Ordered Set is SKP, Receivers of a multi-Lane Link report an error for the Lane(s) in the Lane Error Status register if the received Symbol number 1 through 4N does not match the corresponding Symbol in § Table 4-52 or § Table 4-53.
  • Receiving a Data Block on any Lane when the previous block contained an EDS Token is a Framing Error. It is strongly recommended that Receivers of a multi-Lane Link report an error for the Lane(s) that received the Data Block in the Lane Error Status register.
  • Receivers are permitted to check for different Ordered Sets on different Lanes. For example, Lane 0 receives a SKP Ordered Set and Lane 1 receives an EIOS. If checked, receiving different Ordered Sets is a Framing Error, unless it is a combination of EIEOS/EIOS and SKP OS for L0p transitions.

4.2.2.3.4 Receiver Framing Requirements in Flit Mode

While processing the Data Stream, Receivers must check the Block type received by each Lane, after accounting for Lane-to-Lane de-skew, for the following conditions:

• Not receiving a SKP Ordered Set followed by a Data Block after on any Lane immediately following an SDS Ordered Set is a Framing Error.
• Receiving a Block with an undefined Block type (a Sync Header of 11b or 00b) is a Framing Error. It is strongly recommended that Receivers of a multi-Lane Link report an error for any Lane that received the undefined Block type in the Lane Error Status register.
• For Lanes that are not entering or exiting the electrical idle state as part of L0p state, the following conditions result in a Framing Error. It is strongly recommended that Receivers of a multi-Lane Link report an error for any Lane that caused the Framing Error in the Lane Error Status register.
  • Receiving an Ordered Set Block on any Lane in an unscheduled Block boundary, as defined in § Section 4.2.3.1
  • Not receiving one of these three Ordered Sets of the appropriate length at the scheduled Block boundary: EIEOS, SKP Ordered Set, or EIOS
  • Receivers are permitted to check for different Ordered Sets on different Lanes. For example, Lane 0 receives a SKP Ordered Set and Lane 1 receives an EIOS. If checked, receiving different Ordered Sets is a Framing Error

4.2.2.3.5 Recovery from Framing Errors in Non-Flit Mode and Flit Mode

If a Receiver detects a Framing Error while processing the Data Stream, it must:

• Report a Receiver Error as described in § Section 4.2.5.8 .
• Stop processing the Data Stream. Processing of a new Data Stream is initiated when the next SDS Ordered Set is received as previously described.
• Initiate the error recovery process as described in § Section 4.2.5.8 . If the LTSSM state is L0, direct the LTSSM to Recovery. If the LTSSM state is Configuration.Complete or Configuration.Idle when the Framing Error is detected, the error recovery process is satisfied by either a transition from Configuration.Idle to Recovery.RcvrLock due to the specified timeout, or a transition to Recovery through L0. If the LTSSM state is Recovery.RcvrCfg or Recovery.Idle when the Framing Error is detected, the error recovery process is satisfied by either a transition from Recovery.Idle to Recovery.RcvrLock due to the specified timeout, or a directed transition from L0 to Recovery. If the LTSSM substate is either Recovery.RcvrLock or Configuration.Linkwidth.Start, the error recovery process is satisfied upon exit from these substates and no direction of the LTSSM to Recovery is required.
  • Note: The framing error recovery mechanism is not expected to directly cause any Data Link Layer initiated recovery action such as NAK.

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IMPLEMENTATION NOTE: TIME SPENT IN RECOVERY DUE TO DETECTION OF A FRAMING ERROR
When using 128b/130b encoding, all Framing Errors require Link recovery. It is expected that implementations will require less than 1 microsecond to recover from a Framing Error as measured from the time that both Ports have entered the Recovery state.

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4.2.2.4 Scrambling in Non-Flit Mode and Flit Mode

Each Lane of the transmitter in a multi-Lane Link may implement a separate LFSR for scrambling. Each Lane of the receiver in a multi-Lane Link may implement a separate LFSR for descrambling. Implementations may choose to implement fewer LFSRs but must achieve the same functionality as independent LFSRs.
The LFSR uses the following polynomial: G(X) = X23 + X21 + X16 + X8 + X5 + X2 + 1 and is demonstrated in § Figure 4-18.

The scrambling rules are as follows:

• The two bits of the Sync Header used in 8.0 GT/s, 16.0 GT/s, or 32.0 GT/s Data Rate are not scrambled and do not advance the LFSR.
• All 16 Symbols of an Electrical Idle Exit Ordered Set (EIEOS) bypass scrambling. The scrambling LFSR is initialized after the last Symbol of an EIEOS is transmitted, and the descrambling LFSR is initialized after the last Symbol of an EIEOS is received.
• TS1 and TS2 Ordered Sets for 8.0 GT/s, 16.0 GT/s, or 32.0 GT/s Data Rate:
  • Symbol 0 of a TS1 or TS2 Ordered Set bypasses scrambling.
  • Symbols 1-13 are scrambled.
  • Symbols 14 and 15 bypass scrambling if required for DC Balance, but they are scrambled if not required for DC Balance.
• All 16 Symbols of a Fast Training Sequence (FTS) Ordered Set used in 8.0 GT/s, 16.0 GT/s, or 32.0 GT/s bypass scrambling.
• All 16 Symbols of a Start of Data Stream (SDS) Ordered Set bypass scrambling.
• All 16 Symbols of an Electrical Idle Ordered Set (EIOS) bypass scrambling.
• All Symbols of a SKP Ordered Set bypass scrambling.
• Transmitters advance their LFSR for all Symbols of all Ordered Sets except for the SKP Ordered Set. The LFSR is not advanced for any Symbols of a SKP Ordered Set.
• Receivers evaluate Symbol 0 of Ordered Set Blocks to determine whether to advance their LFSR. If Symbol 0 of the Block is SKP (see § Section 4.2.8.2 ), then the LFSR is not advanced for any Symbol of the Block. Otherwise, the LFSR is advanced for all Symbols of the Block.
• All 16 Symbols of a Data Block are scrambled and advance the scrambler.
• For Symbols that need to be scrambled, the least significant bit is scrambled first and the most significant bit is scrambled last.
• The seed value of the LFSR is dependent on the Lane number assigned to the Lane when the Link first entered Configuration.Idle (i.e., having gone through Polling from Detect with LinkUp = 0b).
  • The seed values for Lane number modulo 8 are:

Lane	Seed
0	1DBFBCh
1	0607BBh
2	1EC760h
3	18C0DBh
4	010F12h
5	19CFC9h
6	0277CEh
7	1BB807h

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IMPLEMENTATION NOTE: SCRAMBLING PSEUDO-CODE
The pseudo-code for the scrambler along with examples are provided in § Section C.2 of § Appendix C. .

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• The seed value of the LFSR does not change while LinkUp=1. Link reconfiguration through the LTSSM Configuration state does not modify the initial Lane number assignment as long as LinkUp remains 1 (even though the Lane assignment may change during Configuration).
• Scrambling cannot be disabled in Configuration.Complete when using 128b/130b encoding.
• A Loopback Follower must not descramble or scramble the looped-back bit stream.
  

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IMPLEMENTATION NOTE: LFSR IMPLEMENTATION WITH A SHARED LFSR
Implementations may choose to implement one LFSR and take different tap points as shown in § Figure 4-19, which is equivalent to the individual LFSR per-lane with different seeds, as shown in § Figure 4-18. It should also be noted that the tap equations of four Lanes are the XOR of the tap equations of two neighboring Lanes. For example, Lane 0 can be obtained by XORing the output of Lanes 1 and 7; Lane 2 is the XOR of Lanes 1 and 3; Lane 4 is the XOR of Lanes 3 and 5; and Lane 6 is the XOR of Lanes 5 and 7. This can be used to help reduce the gate count at the expense of potential delay due to the XOR results of the two Lanes.

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4.2.2.5 Precoding

A Receiver may request precoding from its transmitter for operating at data rates of 32.0 GT/s and higher. Precoding, when enabled at a Data Rate, applies to both Flit Mode and Non-Flit Mode at that data rate. The precoding rules are as follows:

• A Port or Pseudo-Port must request precoding on all configured Lanes of the Link. Behavior is undefined if precoding is requested on some Lanes but not others by a Port or Pseudo-Port.
• A Port or Pseudo-Port may request precoding independent of other Ports or Pseudo-Ports. For example, it is possible that precoding may be turned on only in the Upstream Port in the case with no Retimers in § Figure 4-60, or on all the Lanes in Tx(A) and Tx(E) in the two Retimer example in § Figure 4-60.
• Precoding is turned off for all data rates when the LTSSM is in the Detect state.
• If a precoding request to a target data rate is to be made, it must be made prior to entering that data rate. A precoding request is made by setting the Transmitter Precode Request bit in the EQ TS2 or the 128b/
  130b EQ TS2 Ordered Sets prior to the transition to Recovery.Speed for the target data rate at which the precoding will be turned on. For each data rate of 32.0 GT/s or higher, the precoding request must be made independently.
• Each (pseudo) Port must store the precoding request along with the Tx Eq values from the most recent equalization procedure in each Lane. If the Link operates at 32.0 GT/s or higher data rate without performing equalization through the No Equalization Needed mechanism it negotiated in the TS1/TS2 Ordered Sets or modified TS1/TS2 Ordered Sets or the Link operates at the 32.0 GT/s or higher data rate in Polling.Compliance, the precoding requests from the last equalization results that are being used must be enforced. If no equalization has ever been performed on the Link (prior to the current Link up), then precoding will not be turned on.
• If the Transmitter Precode Request bit is Set to 1b in each of the received eight consecutive EQ TS2 or 128b/ 130b EQ TS2 Ordered Sets during Recovery.RcvrCfg prior to entry to Recovery.Speed, the Transmitter must turn on the precoding for the target data rate at which the Link will operate on exit from Recovery.Speed if the target data rate is 32.0 GT/s or higher. Once turned on, precoding will be in effect for that target data rate until the Transmitter receives another set of eight consecutive EQ TS2 or 128b/130b EQ TS2 Ordered Sets with Transmitter Precode Request set to 0b during Recovery.RcvrCfg prior to entry to Recovery.Speed for the same target data rate.
• A Transmitter must not turn on precoding for any data rates lower than 32.0 GT/s.
• In data rates of 32.0 GT/s or higher, a Transmitter must set the Transmitter Precoding On bit to 1b in the TS1 Ordered Sets that it transmits in Recovery if its precoding is on for the current data rate; else the bit must be set to 0b.
• A Transmitter that has turned on precoding for the 32.0 GT/s data rate on Lane 0 must set the 32.0 GT/s Transmitter Precoding On bit to 1b in the 32.0 GT/s Status Register; else, it must set the bit to 0b. A Receiver that has requested, or will request, its link partner to turn on precoding at the 32.0 GT/s data rate must set the 32.0 GT/s Transmitter Precode Request to 1b in the 32.0 GT/s Status Register; else it must set the bit to 0b.
• A Transmitter that has turned on precoding for the 64.0 GT/s data rate on Lane 0 must set the 64.0 GT/s Transmitter Precoding On bit to 1b in the 64.0 GT/s Status Register; else it must set the bit to 0b. A Receiver that has requested, or will request, its link partner to turn on precoding at the 64.0 GT/s data rate must set the 64.0 GT/s Transmitter Precode Request to 1b in the 64.0 GT/s Status Register; else it must set the bit to 0b.
• See § Section 4.2.2.5.1 for 32.0 GT/s precoding requirements. See § Section 4.2.3.1.4 for 64.0 GT/s and above data rate precoding requirements.

4.2.2.5.1 Precoding at 32.0 GT/s Data Rate

When precoding is on at 32.0 GT/s, the following rules apply (see § Figure 4-20):

• Only scrambled bits are precoded.
• The “previous bit” used for precoding is set to 1b on every block boundary and gets updated by the last scrambled and precoded bit transmitted within the current block boundary.
• For symbols that are scrambled, Receivers must first decode the precoded bits before sending them to the descrambler.

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IMPLEMENTATION NOTE: PARITY IN THE SKP ORDERED SET WHEN PRECODING IS TURNED ON
As per the rules of § Section 4.2.5.1 and § Section 4.2.8.2 , when precoding is turned on, the parity in the SKP Ordered Sets should be calculated before precoding is applied on the Transmit side. Thus, the order in the Transmitter is:

1. scrambling,
2. followed by parity bit calculation,
3. followed by precoding for the scrambled bits.
   Accordingly, in the Receiver, the order is:
4. precoding (if turned on by the Transmitter),
5. followed by parity bit calculation,
6. followed by descrambling.
   The rationale for this order is that in a Link with one or two Retimers, different Link segments may have the precoding on or off. Let us consider an example system with one retimer between the Root Port and End Point to illustrate this. In the upstream direction, the End Point has precoding on in its Transmitter Lanes since the Retimer Receiver needs it but the Retimer to Root Port Link segment has the precoding off since the Root Port does not need precoding at its Receiver. Since the Retimer does not change the parity bit, the Root Port would get a parity error if the parity calculation was done by the Transmitter (of the End Point) after precoding.

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IMPLEMENTATION NOTE: LOOPBACK LEAD’S BEHAVIOR IF PRECODING IS ON IN ANY LINK SEGMENT
As per the rules of precoding mentioned in this section and § Section 4.2.7.4 , a Loopback Lead operating at a data rate of 32.0 GT/s or higher should account for precoding to be on some link segments and off in other link segments. This is particularly relevant when the Loopback Follower transitions from sending TS1 Ordered Sets to looping back the bits. This is where the precoding on the receiver of the Loopback Lead may switch (between precoding on and off). The Loopback Lead is permitted to use implementation specific mechanisms to handle this scenario.

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IMPLEMENTATION NOTE: TS1/TS2 ORDERED SETS WHEN PRECODING IS TURNED ON
As per the rules in this section, when precoding is turned on, the ‘previous bit’ used for precoding is 1b for the first bit of Symbol 1 since Symbol 0 is not scrambled and the ‘previous bit’ gets set to 1b at the block boundary.

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4.2.2.6 Loopback with 128b/130b Code in Non-Flit Mode and Flit Mode

When using 128b/130b encoding, Loopback Leads must transmit Blocks with the defined 01b and 10b Sync Headers. However, they are not required to transmit an SDS Ordered Set when transitioning from Ordered Set Blocks to Data Blocks, nor are they required to transmit an EDS Token when transitioning from Data Blocks to Ordered Set Blocks. Leads must transmit SKP Ordered Sets periodically as defined in § Section 4.2.8 , and they must be capable of processing received (looped-back) SKP Ordered Sets of varying length. Leads are permitted to transmit Electrical Idle Exit Ordered Sets (EIEOS) as defined in § Section 4.2.2.2.1 . Leads are permitted to transmit any payload in Data Blocks and Ordered Set Blocks that they expect to be looped-back. If the Loopback Lead transmits an Ordered Set Block whose first symbol matches the first symbol of SKP OS, EIEOS, or EIOS, that Ordered Set Block must be a complete and valid SKP OS, EIEOS, or EIOS.
When using 128b/130b encoding, Loopback Followers must retransmit all bits received without modification, except for SKP Ordered Sets which can be adjusted as needed for clock compensation. If clock compensation is required, Followers must add or remove 4 SKP Symbols per Ordered Set. The modified SKP Ordered Set must meet the definition of § Section 4.2.8.2 (i.e., it must have between 4 to 20 SKP Symbols followed by the SKP_END Symbol and the three Symbols that follow it as transmitted by the Loopback Leads. If a Follower is unable to obtain Block alignment or it is misaligned, it may be unable to perform clock compensation and therefore unable to loop-back all bits received. In this case, it is permitted to add or remove Symbols as necessary to continue operation. Followers must not check for a received SDS Ordered Set when a transition from Ordered Set Blocks to Data Blocks is detected, and they must not check for a received EDS Token when a transition from Data Blocks to Ordered Set Blocks is detected.

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代码如下（示例）：

data = pd.read_csv(
    'https://labfile.oss.aliyuncs.com/courses/1283/adult.data.csv')
print(data.head())

该处使用的url网络请求的数据。

4.2.3 Flit Mode Operation

Flit definition and Symbol placement is specified in this section.
Flits encoded with 8b/10b encoding follow the rules in § Section 4.2.1 with the following exception:
• Since the Flit Mode has its fixed TLP and DLP placement, the packet markers such as STP, SDP, END, EDB are not used.
Flits Encoded with 128b/130b encoding follow the rules in § Section 4.2.2 with the following exceptions:
• Since the Flit Mode has its fixed TLP and DLP placement, the Framing Tokens are not used.
1b/1b encoding is specified in Section 4.2.3.1.

4.2.3 Flit模式操作
Flit定义和字符位置在本节中指定。
使用8b/10b编码的Flits遵循§4.2.1中的规则，但有以下例外:
•由于Flit模式有固定的TLP和DLP布局，因此不会使用STP、SDP、END、EDB等数据包标记。
使用128b/130b编码的Flits遵循§4.2.2中的规则，但有以下例外:
•由于Flit模式有其固定的TLP和DLP布局，因此不使用帧令牌。
1b/1b编码在章节4.2.3.1中指定。

4.2.3.1 1b/1b Encoding for 64.0 GT/s and higher Data Rates

When the PCI Express Link is operating at 64.0 GT/s or higher Data Rates, it uses Flit Mode. A Symbol (8 bits) is the basic unit of transfer per Lane. PAM4 signaling is used for all Symbols, whether it belongs to a Data Stream or an Ordered Set. PAM4 operates on 2-bit aligned boundaries. A Symbol, represented as ‘S7S6S5S4S3S2S1S0’, is placed on a Lane starting with the voltage encoding of ‘S1S0’ and ending with ‘S7S6’. . An example placement of Flits (described later) or Ordered Set on a x4 Link is shown in § Figure 4-21 below.

4.2.3.1 64.0 GT/s及更高的数据速率下的1b/1b编码
当PCI Express链路运行在64.0 GT/s或更高的数据速率时，它使用Flit模式。Symbol字符(8位)是每信道传输的基本单位。PAM4信令用于所有符号，无论它属于数据流还是有序集。PAM4在2位对齐边界上操作。一个字符，其以“s7s65s5s4s3s2s1s0”表示，其被放置在一条Lane上时，以“S1S0”的电压编码开始、以“S7S6”结束。Flits(稍后将介绍)或Ordered Set在x4 Link上的布局示例如下§图4-21所示。

A conceptual diagram of the Transmit side and Receive side is shown in § Figure 4-22 and § Figure 4-23 respectively. These diagrams are provided to explain the order of operations that must be performed on the Transmit and Receive side. An implementation may choose to operate on different widths depending on the design goals and constraints.

发送端和接收端原理图分别如图4-22和图4-23所示。提供这些图表是为了解释必须在发送端和接收端执行的操作顺序。实现可以根据设计目标和约束选择在不同的宽度上操作。

At a Flit level, on the Transmit side, CRC is first applied followed by FEC generation. After that, each Lane is allotted its Symbol in the byte interleaved fashion for the Flit. On a per Lane basis, Scrambling is performed, if required, followed by Gray Coding at a 2-bit aligned boundary, after which Precoding is performed at 2-bit aligned UI level, if enabled and required. Thus, in the Symbol above, Gray Coding and Precoding will be applied for the bits corresponding to ‘S1S0’,‘S3S2’,…, ‘S7S6’. As shown in the diagram below, the scrambled symbols of the TS1/TS2 Ordered sets also undergo the precoding logic (including bypass). All Symbols, whether they belong to a Flit (Data Stream) or scrambled Symbols of an Ordered Set or any pattern (compliance pattern, fast toggle pattern, high swing jitter pattern, low swing jitter pattern, jitter measurement pattern) undergo the Gray Coding and PAM4 encoding, whereas unscrambled Symbols of an Ordered Set or any pattern only undergo the PAM4 encoding (the gray coding and DC-balance is effectively taken care of through the bit assignment). For the cases where parts of a pattern may be expressed as a repeated sequence of UI to avoid repetition, the Symbol here refers to the aligned 4 UI interval of that pattern.

单个Flit，在发送端，首先计算CRC，然后进行FEC生成。之后，每个Lane上以字节交错的方式为Flit分配其字符。在每个Lane的基础上，如果需要则进行加扰，然后在2位对齐的边界进行灰度编码，之后如果启用和需要、则在2位对齐的UI级别执行预编码。因此，在上面的符号中，将对' S1S0 '， ' S3S2 '，…，' S7S6 '对应的位进行灰度编码和预编码。如下图所示，TS1/TS2有序集的加扰字符也经过预编码逻辑(包括bypass)。所有的字符，无论是属于Flit(数据流)还是加扰的有序集或任何码型(一致性测试码型、快速切换码型、高摆幅抖动码型、低摆幅抖动码型、抖动测量码型)的字符都经过灰色编码和PAM4编码，而有序集或任何码型的未加扰字符只经过PAM4编码(通过位分配有效地处理了灰色编码和dc平衡)。 ?? ”对于模式的某些部分可以表示为重复的UI序列以避免重复的情况，这里的字符指的是该模式的对齐的4个UI间隔。“??

The Receive side is similar to the Transmit side in the opposite direction. After the PAM4 voltage is converted to a 2-bit aligned quantity, it undergoes the Receive side precoding if applicable followed by the decoding of the Gray code, followed by descrambling on a single bit level, if applicable. The Data Stream (Flit) is aggregated across all Lanes and undergoes the FEC decode and correction followed by the CRC check before sending up the Transactions and Data Link Payload.

接收端在相反方向上与发送端相似。在PAM4电压转换为2位对齐量后，如果适用的话，它将先在接收侧进行预编码，然后进行Gray码的解码，如果适用的话，接着是单比特级的解扰。所有通道上的数据流(Flit)进行聚合，在发送事务和数据链路有效载荷之前，经过FEC解码和校正，然后进行CRC检查。

4.2.3.1.1 PAM4 Signaling

PAM4 stands for Pulse Amplitude Modulation 4-levels. It is a signaling mechanism where 4 levels (2 bits) are encoded in same Unit Interval (UI) resulting in 3 eyes, as shown in § Figure 4-24. It is deployed only for 64.0 GT/s or higher Data Rates. As described in § Chapter 8, PAM4 helps with the channel loss as it has the same Nyquist frequency as 32.0 GT/s for 64.0 GT/s Data Rate. The four voltage levels 0, 1, 2, and 3, nominally map to -400 mV, -133 mV, +133 mV and +400 mV respectively, and the Gray code encoded values of 00b, 01b, 11b, and 10b respectively, with the little-endian bit order, as shown in § Figure 4-24. The corresponding DC Balance values to be used when designing Ordered Sets to meet the DC balance needs is also shown in § Figure 4-24. The Reduced voltage levels (eye height or EH) and eye width (EW) increases susceptibility to errors. Gray coding is used to help minimize errors within a UI for the voltage levels.

4.2.3.1.1 PAM4信令
PAM4代表脉冲幅度调制4级。它是一种信令机制，在相同的单位间隔(UI)中、其编码4个级别的电平，从而产生3个眼，如图4-24所示。PAM4仅适用于64.0 GT/s及以上的数据速率。如第8章所述，PAM4有助于减少信道损耗，因为对于64.0 GT/s数据速率，PAM4具有与32.0 GT/s相同的奈奎斯特频率。0、1、2、3四个电压等级，在标称上分别对应-400mv、-133mv、+133mv、+400mv；Gray码分别编码00b、01b、11b、10b的值，位序为小端，如图4-24所示。在设计有序集以满足直流平衡需求时，相应的DC Balance值也如图4-24所示。降低电压水平(眼高或EH)和眼宽(EW)增加了对错误的敏感性。灰度编码用于帮助减少一个UI内电压电平的错误。

With PAM4 encoding, the bit error rate (BER) is expected to be significantly worse than the 10^-12 BER target of the lower data rates (2.5, 5.0, 8.0, 16.0, and 32.0 GT/s). In addition, errors are expected to occur in bursts in a Lane and some amount of Lane to Lane correlation is also expected. The electrical spec parameters along with FBER (First Bit Error Rate) < 10^-6 described in § Chapter 8 must be met to ensure probability of a Flit error after FEC to be less than 3×10^-5.

使用PAM4编码，误码率(BER)预计将明显低于较低数据速率(2.5、5.0、8.0、16.0和32.0 GT/s)的 10^-12 误码率目标。此外，错误预计会在Lane中突发出现，并且Lane到Lane的相关性也会有所增加。第8章中描述的电气规范参数以及FBER(第一比特误码率)< 10^-6必须满足，以确保FEC后的Flit错误概率小于3×10^-5。

A Forward Error Correction (FEC) mechanism is used to deal with the high FBER in the Data Stream. Since FEC works on fixed sized code words, Flit (flow control unit) will be used for sending/ receiving TLPs and DLLPs in a data stream. A low-overhead FEC will be used to keep the latency low. This will be augmented with a strong CRC at Flit level for high reliability. Link level retry will be deployed at the Flit level in Flit Mode. Ordered Sets will be protected through replication for Data Rates of 64.0 GT/s and above. Additionally, the precoding mechanism described below will be used for all scrambled bits to help minimize the number of errors in an error burst within a Lane.

采用前向纠错(Forward Error Correction, FEC)机制来处理数据流中的第一比特误码率。由于FEC在固定大小的编码字数上工作，Flit(流量控制单元)将用于在数据流中发送/接收TLPs和DLLPs。低开销FEC将用于保持低延迟。使用一个强CRC将在Flit级别提高可靠性。在Flit模式下，将在Flit级别上使用链路级重传。对于64.0 GT/s及以上的数据速率，有序集将通过重复得到保护。此外，下面描述的预编码机制将用于所有的加扰位，以帮助减少在一个Lane内的错误突发中的错误数量。

4.2.3.1.2 1b/1b Scrambling

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8.4.5.5 Electrical Idle

Electrical Idle is a steady state condition where the Transmitter D+ and D- voltages are held constant at the same value. Electrical Idle is primarily used in power saving and inactive states (e.g., Disabled).

Before a Transmitter enters Electrical Idle, it must always send the required number of EIOSs except for the LTSSM substates explicitly exempted from this requirement. After sending the last Symbol of the last of the required number of EIOSs, the Transmitter must be in a valid Electrical Idle state within the time as specified by TTX-IDLE-SET-TO-IDLE in § Table
8-7 .

The successful reception of an EIOS occurs based on the rules defined in the Physical Layer Logical Block chapter. It should be noted that in substates (e.g., Loopback.Active for a Loopback Follower ) where multiple consecutive EIOSs are expected, the Receiver must receive the appropriate number of EIOS sequences comprising of COM, IDL, IDL, IDL.

The low impedance common mode and differential Receiver termination values (see § Table 8-7 and § Table 8-12 ) must be met in Electrical Idle. The Transmitter can be in either a low or high impedance mode during Electrical Idle.

Any time a Transmitter enters Electrical Idle it must remain in Electrical Idle for a minimum of TTX-IDLE-MIN . The Receiver should expect the last EIOS followed by a minimum amount of time in Electrical Idle ( TTX-IDLE-MIN ) to arm its Electrical Idle Exit detector.

When the Transmitter transitions from Electrical Idle to a valid differential signal level it must meet the output return loss specifications described in § Figure 8-22 , § Figure 8-24 , § Figure 8-23 , and § Figure 8-25 .

Electrical Idle Exit shall not occur if a signal smaller than VRX-IDLE-DET-DIFFp-p minimum is detected at a Receiver. Electrical Idle Exit shall occur if a signal larger than VRX-IDLE-DET-DIFFp-p maximum is detected at a Receiver. Electrical Idle may be detected on the received signal regardless of its frequency components, or it may be detected only when the received signal is switching at a frequency of 125 MHz or higher.

8.4.5.5 电气空闲
电气空闲时一种稳定状态，其间发送端的D+和D-电压持续维持在相同值。电气空闲主要用于节省功率以及未激活状态（即，Disabled状态）。
在发送端进入电气空闲状态前，发送端必须发送要求数目的EIOSs，除非LTSSM的子状态明确豁免此要求。在发送最后一个要求数目的EIOSs的最后一个字符后，发送端必须在表8-7中TTX-IDLE-SET-TO-IDLE(max:8ns)所规定的时间内进入到一个有效的电气空闲状态。
成功接收到一个EIOS的规则，定义在物理层逻辑子层一章中。需要注意的是，在子状态中多个连续的EIOS预期应该受到，此时接收端必须收到适当数目的由COM、IDL、IDL、IDL组成的EIOS序列。
在电气空闲状态中，接收端必须满足低阻抗共模和差分的接收端数值（见表8-7和表8-12）。在电气空闲状态，发送端既可以处于低阻模式，也可以处于高阻模式。
每次发送端进入电气空闲状态时，都必须在TTX-IDLE-MIN(min:20ns)的最小值的时间内处于电气空闲状态。接收端应该预期在收到最后一个EIOS后的电气空闲最小时间内，让它的电气空闲退出探测器工作起来。
当发送端从电气空闲跳转到一个有效的差分信号电平时，必须满足图8-22、图8-24、图8-23和图8-25中所述的输出回损规范。
电气空闲退出不应出现在，接收端探测到一个低于VRX-IDLE-DET-DIFFp-p([60-175]mV)最小值的信号时。电气空闲退出应出现在，接收端探测到一个大于VRX-IDLE-DET-DIFFp-p最大值的信号时。无论接收信号的频率成分如何，都可以在其上检测到电气空闲，或者仅当接收信号以125 MHz或更高的频率切换时才可以检测到电空闲。