PCIE 6.1：8.6 Refclk Specifications 原文+译文

原文

8.6 Refclk Specifications

This version of the specification consolidates and streamlines the Refclk requirements. The 2.5 GT/s Refclk parameters are moved from the CEM spec to this spec so that all Refclk parameters for all data rates (2.5, 5.0, 8.0, 16.0, 32.0, and 64.0 GT/s) are now contained in this section.

8.6.1 Refclk Test Setup

The test setup for the Refclk assumes that only the Refclk generator itself is present. Provision is made in the test setup to account for signal degradation that occurs between the pins of the Refclk generator and the Transmitter or Receiver in an actual system. The above described setup emulates the worst case signal degradation that is likely to occur at the pins of a PCI Express device. Note that the Refclk signal is tested into a load that represents the series (open) termination appearing at the Refclk input pins of a PCIe device for all requirements except 32.0 and 64.0 GT/s reference clock jitter. For 32.0 and 64.0 GT/s, the reference clock jitter is measured with an oscilloscope, and is tested with the reference clock terminated by 50 Ohm terminations without a channel.

Figure 8-80 Oscilloscope Refclk Test Setup for All Cases Except Jitter at 32.0 and 64.0 GT/s

8.6.2 REFCLK AC Specifications

All specifications in § Table 8-18 are to be measured using a test configuration as described in Note 11 with a circuit as shown in § Figure 8-80.

Table 8-18 REFCLK DC Specifications and AC Timing Requirements

Symbol	Parameter	100 MHz Input（Min）	100 MHz Input （Max）	Unit	Note
Rising Edge Rate	Rising Edge Rate	0.6	4.0	V/ns	2, 3
Falling Edge Rate	Falling Edge Rate	0.6	4.0	V/ns	2, 3
VIH	Differential Input High Voltage	+150		mV	2
VIL	Differential Input Low Voltage		-150	mV	2
VCROSS	Absolute crossing point voltage	+250	+550	mV	1, 4, 5
VCROSS DELTA	Variation of VCROSS over all rising clock edges	+140	mV	1, 4, 9
VRB	Ring-back Voltage Margin	-100	+100	mV	2, 12
TSTABLE	Time before VRB is allowed	500	ps	2, 12
TPERIOD AVG	Average Clock Period Accuracy	-300	+2800	ppm	2, 10, 13
TPERIODAVG_32G_64G_CC	Average Clock Period Accuracy for devices that support 32.0 and 64.0 GT/s in CC Mode at any speed	-100	2600	ppm	2, 10, 13

原文

8.6 参考时钟规范

这个版本的规范整合并简化了参考时钟要求。2.5 GT/s的Refclk参数从CEM规范移到了本规范中，因此所有数据速率(2.5、5.0、8.0、16.0、32.0和64.0 GT/s)的Refclk参数现在都包含在本节中。

8.6.1 参考时钟测试设备

参考时钟的测试设置假设只有参考时钟生成器本身存在。在测试设置中提供了考虑实际系统中Refclk发生器和发射器或接收器的引脚之间发生的信号衰减的规定。上面描述的设置模拟了可能发生在PCI Express设备的引脚处的最坏情况下的信号衰减。请注意，除了32.0 GT/s和64.0 GT/s参考时钟抖动外，Refclk信号被测试成一个负载，该负载代表在PCIe设备的Refclk输入引脚处出现的系列(打开)终端。对于32.0 GT/s和64.0 GT/s，使用示波器测量参考时钟抖动，并使用无通道的50欧姆终端对参考时钟进行测试。

图8-80 示波器参考时钟测试设备（适用于除了32.0和64.0 GT/s的所有情况）

8.6.2 参考时钟交流规范

表8-18中的所有规范都要使用注11中描述的测试配置和图8-80中所示的电路进行测量。