本文提供了2023年AMD芯片设计工程师笔试的题目回顾，包含15道单选题、6道多选题及1道问答题，涵盖SystemVerilog、ARM AMBA AHB协议、数字IC设计等多个方面。难度适中，适合刷题和复习。
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题目背景
- 笔试时间：2022.09.12
- 应聘岗位：芯片设计工程师 ASIC Design Engineer
- 笔试时长：60min
- 笔试平台：ShowMeBug
- 题目类型：单选题（15道）、多选题（6道）、问答（1道）
主观评价
- 难易程度：★★★☆☆
- 知识覆盖：★★☆☆☆
- 超纲范围：★★☆☆☆
- 值得一刷：★★★☆☆
文章目录
- 单选题
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- 1 Which of the following can not reduce static power consumption?
- 2 For below System Verilog code, select the output result: ()
- 3 How many timing paths in the picture? ()
- 4 Which of the following circuits can set false_path:
- 5 In ARM AMBA AHB protocol, which of following responses is ONE cycle response?
- 6 Which logic is not the sequence logic?
- 7 If the following program enters "1" the output is ()
- 8 Which one is the first step to start the verification?
- 9 Which one can be used to represent the same coverage bin as "bins sa =( 3[->3] )" in SV: ()
- 10 Which of the following gates is universal which can be used to construct any Boolean function without any other type of gates?
- 11 In SystemVerilog, the new operation in the following array that needs to be per formed before use is ()
- 12 Which technique be used to avoid control hazards in RISC pipeline?
- 13 Regarding to the UVM and SystemVerilog, which of the following statements is incorrect:
- 14 Which of the following is not a dynamic array built- in function:
- 15 To implement an FSM which has 5 states, at least how many DFFS is needed to use?
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- 多选题
- 问答题
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