Feedthrough

最新推荐文章于 2024-07-26 17:30:15 发布

Daniel雨林

最新推荐文章于 2024-07-26 17:30:15 发布

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分类专栏： Verilog FPGA

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设计中出现同一模块input port和output port直接相连（feedthrough)。

Check for feedthroughs in the design [Design-wide].

Description:

This rule checks for feedthroughs in the design. A feedthrough occurs when an output of a module is exactly the same as an input. This is a design-wide check since input-to-output path may pass through instances. Here the longest feedthrough path is reported as the primary violation and in the associated violations intermediate points are reported. For example, in the following design:

There is a feedthough path from port 'b' to port 'e' in design unit 'Mid' and there is a smaller feedthrough path from port 'c' to port 'd' in design unit 'Bot'. But the smaller feedthough is actually just a part of the longer feedthough path. Hence in the primary violation feedthough path from port 'b' to port 'e' is reported and in associated violations points corresponding to ports 'c' and 'd' are reported.

Languages:

All (Including SystemVerilog)

Parameters:

None

Usage Examples:

Example 1:

Checking for feedthrough paths in designs.

Rule Configuration

Language: Any