Verilog练习一【奇数分频器】

练习：实现50%占空比的5分频

//5分频，占空比为50%
module clk_div_5(Clk_in, Rst_n, Clk_out);
	input Clk_in;
	input Rst_n;
	output Clk_out;
	
	reg [2:0] cnt, cnt1;
	reg clk_p, clk_n;
	
	parameter CNT_M = 3'd4,//N-1   
			  CNT_N = 3'd2;//(N-1)/2
		
	always @(posedge Clk_in) begin //上升沿 5 分频，占空比为 2/5
		if(!Rst_n) begin
			cnt <= 0;
			clk_p <= 0;
		end
		else begin
			if( cnt == CNT_M ) begin
				cnt <= 0;
				clk_p <= ~clk_p;
			end
			else begin
				cnt <= cnt + 1'b1;
				if ( cnt == CNT_N )
					clk_p <= ~clk_p;
				else
					clk_p <= clk_p;
			end
		end
	end
	
	always @(negedge Clk_in) begin //下降沿 5 分频，占空比为 2/5
		if(!Rst_n) begin
			cnt1 <= 0;
			clk_n <= 0;
		end
		else begin
			if( cnt1 == CNT_M ) begin
				cnt1 <= 0;
				clk_n <= ~clk_n;
			end
			else begin
				cnt1 <= cnt1 + 1'b1;
				if ( cnt1 == CNT_N )
					clk_n <= ~clk_n;
				else
					clk_n <= clk_n;
			end
		end
	end
	assign Clk_out = clk_p | clk_n; //错位相或
endmodule

仿真结果：