（23）ISE14.7 PLL输出时钟不能直接输出到普通IO（FPGA不积跬步101）

1 问题描述

开发软件：ISE14.7。
硬件平台：Xilinx Spartan6。
PLL的时钟直接连接到IO，map失败是报错误，错误如下：
Place:1136 - This design contains a global buffer instance, <system_clk_BUFGP/BUFG>, driving the net, <ila0_clk>, that is driving the following (first 30) non-clock load pins.
< PIN: dac8811_top_inst/dac8811_spi_inst/dac_clk_reg11.A5; >
This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations.  It is recommended to only use a BUFG resource to drive clock loads. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue.
< PIN "system_clk_BUFGP/BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; >

从错误可以看出，Xilinx推荐设置伪路径解决该错误。

2 解决方法<