Preblem 29: alwaysblock1
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output wire out_alwaysblock
);
assign out_assign = a & b;
assign out_alwaysblock = a & b;
endmodule
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign = a ^ b;
always @(*)
out_always_comb = a ^ b;
always @(posedge clk)
out_always_ff <= a ^ b;
endmodule
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign = sel_b1?sel_b2? b:a:a;
always @(*)
if(sel_b1 & sel_b2) begin
out_always = b;
end
else begin
out_always = a;
end
endmodule
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else
keep_driving = 0;
end
endmodule
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3'b000 : out = data0;
3'b001 : out = data1;
3'b010 : out = data2;
3'b011 : out = data3;
3'b100 : out = data4;
3'b101 : out = data5;
default : out = 4'b0000;
endcase
end
endmodule
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos );
always @(*)
case(in)
4'b0000: pos = 2'b00;
4'b0001: pos = 2'b00;
4'b0010: pos = 2'b01;
4'b0011: pos = 2'b00;
4'b0100: pos = 2'b10;
4'b0101: pos = 2'b00;
4'b0110: pos = 2'b01;
4'b0111: pos = 2'b00;
4'b1000: pos = 2'b11;
4'b1001: pos = 2'b00;
4'b1010: pos = 2'b01;
4'b1011: pos = 2'b00;
4'b1100: pos = 2'b10;
4'b1101: pos = 2'b00;
4'b1110: pos = 2'b01;
4'b1111: pos = 2'b00;
endcase
endmodule
// synthesis verilog_input_version verilog_2001
module top_module (
input [7:0] in,
output reg [2:0] pos );
always @(*) begin
casez(in)
8'bzzzzzzz1: pos = 0;
8'bzzzzzz1z: pos = 1;
8'bzzzzz1zz: pos = 2;
8'bzzzz1zzz: pos = 3;
8'bzzz1zzzz: pos = 4;
8'bzz1zzzzz: pos = 5;
8'bz1zzzzzz: pos = 6;
8'b1zzzzzzz: pos = 7;
default: pos = 0;
endcase
end
endmodule
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always @(*)begin
up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
case(scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right = 1'b1;
16'he075: up = 1'b1;
endcase
end
endmodule
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
wire [7:0] intermediate_result1;
wire [7:0] intermediate_result2;
assign intermediate_result1 = a < b? a:b;
assign intermediate_result2 = c < d? c:d;
assign min = intermediate_result1 < intermediate_result2 ? intermediate_result1:intermediate_result2;
// assign intermediate_result1 = compare? true: false;
endmodule
module top_module (
input [7:0] in,
output parity);
assign parity = ^ in;
endmodule
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
endmodule
module top_module(
input [99:0] in,
output [99:0] out
);
int i ;
always @(*) begin
for(i=0;i<100;i++)begin
out[i] = in[99-i];
end
end
endmodule
module top_module(
input [254:0] in,
output [7:0] out );
int i;
always @(*)begin
out = 8'b0000_0000;
for(i=0;i<=254;i++)begin
if(in[i] == 1'b1)
out = out + 1'b1;
else
out = out + 1'b0;
end
end
endmodule
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
assign {cout[0],sum[0]} = a[0] + b[0] + cin;
int i;
always @(*) begin
for(i=1;i<=99;i++)begin
{cout[i],sum[i]} = a[i] + b[i] + cout[i-1];
end
end
endmodule
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire [399:0] cout_tem;
genvar i;
bcd_fadd bcd1 (a[3:0],b[3:0],cin,cout_tem[0],sum[3:0]);
generate
for(i=4;i<=399;i=i+4)
begin:bcd
bcd_fadd bcdt(a[i+3:i],b[i+3:i],cout_tem[i-4],cout_tem[i],sum[i+3:i]);
end
endgenerate
assign cout = cout_tem[396];
endmodule
module top_module (
input in,
output out);
assign out = in;
endmodule
module top_module (
output out);
assign out = 1'b0;
endmodule
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
module top_module (
input in1,
input in2,
output out);
assign out = in1 & (~in2);
endmodule
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
Preblem 49:gates
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a &(~b);
endmodule
Preblem 50:7420
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = ((~x3) & x2 & (~x1)) | ((~x3) & (x2) & (x1)) | (x3 & (~x2) & x1) | (x3 & x2 & x1);
endmodule
module top_module ( input [1:0] A, input [1:0] B, output z );
assign z = (A == B) ? 1'b1 :1'b0 ;
endmodule
module top_module (input x, input y, output z);
assign z = (x ^ y) & x;
endmodule
module top_module ( input x, input y, output z );
assign z = ((~x) & (~y)) | (x & y);
endmodule
module top_module (input x, input y, output z);
wire z1,z2,z3,z4,z5,z6;
assign z1 = (x ^ y) & x;
assign z2 = x ~^ y;
assign z3 = (x ^ y) & x;
assign z4 = x ~^ y;
assign z5 = z1 | z2;
assign z6 = z3 & z4;
assign z = z5 ^ z6;
endmodule
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ~vibrate_mode & ring;
assign motor = vibrate_mode & ring;
endmodule
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = too_cold & mode;
assign aircon = too_hot & (~mode);
assign fan = (too_cold & mode) | (too_hot & (~mode)) | fan_on;
endmodule
module top_module(
input [2:0] in,
output [1:0] out );
int i;
always @(*)begin
out = 2'b0;
for(i = 0;i <= 2;i++)begin
out = out + in[i];
end
end
endmodule
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
int i,j,k;
always @(*)begin
for(i=0;i<=2;i++)
out_both[i] = in[i] & in[i+1];
for(j=1;j<=3;j++)
out_any[j] = in[j] | in[j-1];
for(k=0;k<=3;k++)begin
if(k==3)
out_different[k] = in[k] ^ in[0];
else
out_different[k] = in[k] ^ in[k+1];
end
end
endmodule
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
int i,j,k;
always @(*)begin
for(i=0;i<=2;i++)
out_both[i] = in[i] & in[i+1];
for(j=1;j<=3;j++)
out_any[j] = in[j] | in[j-1];
for(k=0;k<=3;k++)begin
if(k==3)
out_different[k] = in[k] ^ in[0];
else
out_different[k] = in[k] ^ in[k+1];
end
end
endmodule
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
int i,j,k;
always @(*)begin
for(i=0;i<=98;i++)
out_both[i] = in[i] & in[i+1];
for(j=1;j<=99;j++)
out_any[j] = in[j] | in[j-1];
for(k=0;k<=99;k++)begin
if(k==99)
out_different[k] = in[k] ^ in[0];
else
out_different[k] = in[k] ^ in[k+1];
end
end
endmodule
module top_module(
input a, b, sel,
output out );
assign out = sel? b : a;
endmodule
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = sel? b:a;
endmodule
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*)begin
case(sel)
4'b0000: out = a;
4'b0001: out = b;
4'b0010: out = c;
4'b0011: out = d;
4'b0100: out = e;
4'b0101: out = f;
4'b0110: out = g;
4'b0111: out = h;
4'b1000: out = i;
default: out = {16{1'b1}};
endcase
end
endmodule